Controlling a processor resource based on a compile-time prediction of number of instructions-per-cycle that will be executed across plural cycles by the processor
A method, for use in a processor, includes estimating a number of instructions-per-cycle that will be executed by the processor based on static compile-time information extracted during compilation, and controlling a resource of the processor based on the estimated number of instructions-per-cycle. The resource may be a component of the processor that is controlled by throttling or deactivating the component.
1. A method, for use in a processor, the method comprising:
estimating a number of instructions-per-cycle that will be executed across plural cycles by the processor based on static compile-time information extracted during compilation, wherein an estimated number of instructions-per-cycle comprises a compile-time prediction of likely instructions executed per-cycle at run-time for a segment of code; and
controlling a resource of the processor based on the estimated number of instructions-per-cycle.
2. The method of claim 1 , wherein the resource comprises components of the processor; and
wherein controlling comprises deactivating at least one of the components.
3. The method of claim 2 , wherein deactivating is performed by clock gating the at least one component.
4. The method of claim 1 , wherein the resource comprises components of the processor; and
controlling comprises throttling at least one of the components.
5. The method of claim 4 , wherein throttling comprises adaptively changing a number of instructions that are processed by the at least one component.
6. The method of claim 1 , wherein the resource comprises at least one of fetch, decode, execute, issue, and writeback logic units.
7. The method of claim 6 , wherein controlling comprises throttling the fetch unit.
8. The method of claim 1 , wherein estimating is performed speculatively based on an architecture of the processor.
9. The method of claim 1 , further comprising:
providing data in an instruction that controls the resource, the data indicating whether or not to control the resource;
wherein controlling is performed in response to the data.
10. The method of claim 9 , wherein:
controlling is performed in response to data in multiple instructions; and
the data comprises at least one additional bit in each of the multiple instructions.
11. The method of claim 10 , wherein the data comprises plural bits in the multiple instructions.
12. The method of claim 9 , wherein:
controlling is performed in response to data in multiple instructions; and
the data comprises at least one additional bit in less than all of the multiple instructions.
13. The method of claim 12 , wherein the data comprises plural bits in less than all of the instructions.
14. The method of claim 1 , wherein estimating comprises determining instruction-level parallelism in the instructions using the static compile-time information.
15. The method of claim 14 , wherein determining comprises locating instructions that can be executed independently at run-time by the processor.
16. The method of claim 15 , wherein independent instructions are located by performing dependence testing on the instructions.
17. The method of claim 1 , wherein estimating comprises determining loop-level parallelism in the instructions using the static compile-time information.
18. The method of claim 17 , wherein determining comprises locating loops in the instructions.
19. The method of claim 18 , wherein the loops are located by:
retrieving a predetermined number of instructions; and
examining the predetermined number of instructions for indications of loops.
20. The method of claim 1 , wherein estimating takes into account loop-level parallelism in the instructions if an architecture of the processor makes it possible to detect loop-level parallelism at run-time.
21. The method of claim 1 , wherein estimating comprises:
estimating instruction-level parallelism in the instructions; and
estimating loop-level parallelism in the instructions.
22. The method of claim 1 , wherein estimating comprises analyzing a block of instructions to estimate independent instructions that can be executed in parallel.
23. The method of claim 1 , wherein controlling comprises cutting-off a level of voltage to the resource.
24. The method of claim 1 , wherein estimating comprises analyzing memory accesses in the instructions to estimate independent memory accesses.
25. A processor framework comprising:
a compiler which estimates a number of instructions-per-cycle that will be executed across plural cycles by a processor based on static compile-time information extracted during compilation, wherein an estimated number of instructions-per-cycle comprises a compile-time prediction of likely instructions executed per-cycle at run-time for a segment of code; and
a microarchitecture which controls a resource of the processor based on the estimated number of instructions-per-cycle.
26. The processor framework of claim 25 , wherein the resource comprises components of the processor; and
wherein controlling comprises deactivating at least one of the components.
27. The processor framework of claim 26 , wherein deactivating is performed by clock gating the at least one component.
28. The processor framework of claim 25 , wherein the resource comprises components of the processor; and
controlling comprises throttling at least one of the components.
29. The processor framework of claim 28 , wherein throttling comprises adaptively changing a number of instructions that are processed by the at least one component.
30. The processor framework of claim 25 , wherein the resource comprises at least one of fetch, decode, execute, issue, and writeback logic units.
31. The processor framework of claim 30 , wherein controlling comprises throttling the fetch unit.
32. The processor framework of claim 25 , wherein estimating is performed speculatively based on an architecture of the processor.
33. The processor framework of claim 25 , further comprising:
an instruction set architecture that includes data in an instruction that controls the resource, the data indicating whether or not to control the resource;
wherein controlling is performed in response to the data.
34. The processor framework of claim 33 , wherein:
controlling is performed in response to data in multiple instructions; and
the data comprises at least one additional bit in each of the multiple instructions.
35. The processor framework of claim 34 , wherein the data comprises plural bits in the multiple instructions.
36. The processor framework of claim 33 , wherein:
controlling is performed in response to data in multiple instructions; and
the data comprises at least one additional bit in less than all of the multiple instructions.
37. The processor framework of claim 36 , wherein the data comprises plural bits in less than all of the instructions.
38. The processor framework of claim 25 , wherein estimating comprises determining instruction-level parallelism in the instructions using the static compile-time information.
39. The processor framework of claim 38 , wherein determining comprises locating instructions that can be executed independently at run-time by the processor.
40. The processor framework of claim 39 , wherein independent instructions are located by performing dependence testing on the instructions.
41. The processor framework of claim 25 , wherein estimating comprises determining loop-level parallelism in the instructions using the static compile-time information.
42. The processor framework of claim 41 , wherein determining comprises locating loops in the instructions.
43. The processor framework of claim 42 , wherein the loops are located by:
retrieving a predetermined number of instructions; and
examining the predetermined number of instructions for indications of loops.
44. The processor framework of claim 25 , wherein estimating takes into account loop-level parallelism in the instructions if an architecture of the processor makes it possible to detect loop-level parallelism at run-time.
45. The processor framework of claim 25 , wherein estimating comprises:
estimating instruction-level parallelism in the instructions; and
estimating loop-level parallelism in the instructions.
46. The processor framework of claim 25 , wherein estimating comprises analyzing a block of instructions to estimate independent instructions that can be executed in parallel.
47. The processor framework of claim 25 , wherein controlling comprises cutting-off a level of voltage to the resource.
48. The processor framework of claim 25 , wherein estimating comprises analyzing memory accesses in the instructions to estimate independent memory accesses.
49. A device comprising:
a microarchitecture which controls a resource of the device based on an estimated number of instructions-per-cycle, the estimated number of instructions-per-cycle being determined by a compiler which estimates a number of instructions-per-cycle that will be executed by the device across plural cycles based on static compile-time information extracted during compilation, wherein the estimated number of instructions-per-cycle comprises a compile-time prediction of likely instructions executed per-cycle at run-time for a segment of code.
50. The device of claim 49 , wherein the resource comprises at least one of a fetch unit and a functional unit.
51. A method, for use in a processor, the method comprising:
estimating a number of instructions-per-cycle that will be executed by the processor across plural cycles based on static compile-time information extracted during compilation, wherein an estimated number of instructions-per-cycle comprises a compile-time prediction of likely instructions executed per-cycle at run-time for a segment of code;
adding, to an instruction stream executed by the processor, information relating to the estimated number of instructions-per-cycle; and
controlling a resource of the processor based on the information.