IP Library Granted Patent US 11,681,533
Granted Patent B2
US 11,681,533 · App. 16/443,593 · Granted Jun 20, 2023

Restricted speculative execution mode to prevent observable side effects

Inventors: Ron Gabor (Herzliya, IL); Alaa Alameldeen (Hillsboro, OR); Abhishek Basak (Hillsboro, OR); Fangfei Liu (Hillsboro, OR); Francis McKeen (Portland, OR); Joseph Nuzman (Haifa, IL); Carlos Rozas (Portland, OR); Igor Yanover (Yokneam Illit, IL); Xiang Zou (Hillsboro, OR)
Assignee: Intel Corporation
G06F9/3842G06F9/30043G06F9/30047G06F9/30101G06F9/30189G06F12/1027G06F21/57G06F2212/68G06F2221/034
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Quick Facts
Patent No.
US 11,681,533
App. No.
16/443,593
Granted
Jun 20, 2023
Kind
B2
Abstract

Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.

Claims (28)

1. A processor comprising:

configuration storage to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode;

an execution circuit to perform speculative execution; and

a controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled, wherein restricting speculative execution includes preventing training of a hardware prefetcher based on a prefetch operation without preventing the prefetch operation, and wherein the prefetch operation trains the hardware prefetcher while in a non-restricted speculative execution mode.

2. The processor of claim 1 , wherein speculative execution is restricted to prevent the speculative execution from leaving persistent observable side effects.

3. The processor of claim 1 , wherein the controller is to split an operation related to the speculative execution into a first part for forward progress and a second part for performance.

4. The processor of claim 1 , wherein the controller is to determine that a speculation frontier is reached.

5. The processor of claim 4 , wherein the controller is to restrict the speculative execution until the speculation frontier is reached.

6. The processor of claim 4 , wherein the controller is to allow the speculative execution after the speculation frontier is reached.

7. The processor of claim 1 , wherein restricting speculative execution includes restricting a load operation.

8. The processor of claim 1 , wherein restricting speculative execution includes restricting a store operation.

9. The processor of claim 1 , wherein restricting speculative execution also includes preventing the prefetch operation.

10. The processor of claim 1 , wherein restricting speculative execution includes restricting a branch operation.

11. The processor of claim 10 , further comprising a branch prediction unit (BPU) or an instruction fetch unit (IFU), wherein restricting the branch operation includes preventing training of the BPU or re-steering of the IFU based on the branch operation.

12. A method comprising:

enabling a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode;

fetching an instruction for execution by the processor; and

restricting speculative execution of an operation related to the instruction when the restricted speculative execution mode is enabled, wherein restricting speculative execution includes preventing training of a hardware prefetcher based on a prefetch operation without preventing the prefetch operation, and wherein the prefetch operation trains the hardware prefetcher while in a non-restricted speculative execution mode.

13. The method of claim 12 , further comprising:

determining that a speculation frontier has been reached with respect to the operation; and

completing the operation.

14. A system comprising:

a system memory; and

a processor including:

configuration storage to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode;

an execution circuit to perform speculative execution; and

a controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled, wherein restricting speculative execution includes preventing training of a hardware prefetcher based on a prefetch operation without preventing the prefetch operation, and wherein the prefetch operation trains the hardware prefetcher while in a non-restricted speculative execution mode.

15. The system of claim 14 , wherein speculative execution is restricted to prevent the speculative execution from leaving persistent observable side effects in the system.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2019
From: GABOR, RON; ALAMELDEEN, ALAA; BASAK, ABHISHEK; LIU, FANGFEI; MCKEEN, FRANCIS; NUZMAN, JOSEPH; ROZAS, CARLOS; YANOVER, IGOR; ZOU, XIANG
To: INTEL CORPORATION
Reel/Frame 049912/0755 →
Continuity (2)
Provisional Application 62810288 · Feb 25, 2019
Related Publication 20200272474A1 · Aug 27, 2020