Structures with deep trench isolation regions for a high-voltage field-effect transistor
Structures for a high-voltage field-effect transistor that include a deep trench isolation region and methods of forming such structures. The structure comprises a semiconductor substrate, a semiconductor layer on the semiconductor substrate, and a doped layer between the semiconductor layer and the semiconductor substrate. The structure further comprises a trench isolation region including a metal layer that extends through the semiconductor layer and the doped layer into the semiconductor substrate.
1. A structure comprising:
a semiconductor substrate;
a semiconductor layer on the semiconductor substrate;
a doped region in the semiconductor layer;
a doped layer between the semiconductor layer and the semiconductor substrate;
a first trench isolation region including a metal layer that extends through the semiconductor layer and the doped layer into the semiconductor substrate; and
an interconnect structure including a metal feature, a first contact extending from the metal feature to the doped region, and a second contact extending from the metal feature to the metal layer of the first trench isolation region.
2. The structure of claim 1 wherein the metal layer of the first trench isolation region comprises tungsten.
3. The structure of claim 1 wherein the first trench isolation region includes a dielectric layer laterally positioned between the metal layer and the semiconductor layer.
4. The structure of claim 3 wherein the dielectric layer of the first trench isolation region is also laterally positioned between the metal layer and the doped layer.
5. The structure of claim 4 wherein the semiconductor substrate has a first conductivity type, and the semiconductor layer and the doped layer have a second conductivity type that is different from the first conductivity type.
6. The structure of claim 3 wherein the first trench isolation region includes a liner laterally positioned between the metal layer and the dielectric layer.
7. The structure of claim 6 wherein the metal layer comprises a first metal and the liner comprises a second metal different from the first metal.
8. The structure of claim 6 wherein the metal layer of the first trench isolation region comprises tungsten, and the liner comprises titanium, titanium nitride, or a combination thereof.
9. The structure of claim 3 wherein the metal layer of the first trench isolation region includes an end portion inside the semiconductor substrate, and further comprising:
a conductive region between the end portion of the metal layer of the first trench isolation region and the semiconductor substrate.
10. The structure of claim 1 wherein the metal layer of the first trench isolation region includes an end portion inside the semiconductor substrate.
11. The structure of claim 10 further comprising:
a conductive region between the end portion of the metal layer of the first trench isolation region and the semiconductor substrate.
12. The structure of claim 11 wherein the conductive region comprises a silicide.
13. The structure of claim 10 further comprising:
a device structure; and
a second trench isolation region comprising a dielectric material, the second trench isolation region including an end portion in the semiconductor substrate, and the end portion of the second trench isolation region laterally between the end portion of the first trench isolation region and a portion of the semiconductor substrate beneath the device structure.
14. The structure of claim 13 wherein the device structure includes a source/drain region in the semiconductor layer and a gate.
15. The structure of claim 13 wherein the end portion of the first trench isolation region extends to a greater depth in the semiconductor substrate than the second trench isolation region.
16. The structure of claim 1 wherein the doped region and the semiconductor layer have a first conductivity type, and the semiconductor substrate has a second conductivity type different from the first conductivity type.
17. The structure of claim 16 wherein the semiconductor substrate is configured to be coupled to a ground potential.
18. The structure of claim 1 wherein the metal layer of the first trench isolation region includes an end portion inside the semiconductor substrate.
19. The structure of claim 18 further comprising:
a conductive region between the end portion of the metal layer of the first trench isolation region and the semiconductor substrate, the conductive region comprising a silicide.
20. A method comprising:
forming a semiconductor layer on a semiconductor substrate;
forming a doped layer between the semiconductor layer and the semiconductor substrate;
forming a trench isolation region including a metal layer that extends through the semiconductor layer and the doped layer into the semiconductor substrate;
forming a doped region in the semiconductor layer; and
forming an interconnect structure including a metal feature, a first contact extending from the metal feature to the doped region, and a second contact extending from the metal feature to the metal layer of the trench isolation region.