IP Library › Granted Patent US 12,740,359
Granted Patent B2
US 12,740,359 · App. 18/909,876 · Granted Sep 15, 2026

Manufacturing method of semiconductor structure

Inventors: Hsiao-Chiang Lin (New Taipei City, TW); Yoshihiro Nomura (Hsinchu, TW); Chao Wen Huang (Hsinchu, TW)
Assignee: Powerchip Semiconductor Manufacturing Corporation
H10P50/695H10P52/402H10P52/403H10P76/2041H10W20/056H10W20/082H10W46/00
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Quick Facts
Patent No.
US 12,740,359
App. No.
18/909,876
Granted
Sep 15, 2026
Kind
B2
Abstract

A manufacturing method of a semiconductor structure including following steps is provided. A patterned photoresist layer is formed on a substrate by a lithography process. The patterned photoresist layer includes a first opening and a second opening. The first opening includes a first inclined sidewall. An etching process is performed on the substrate by using the patterned photoresist layer as a mask to form a third opening corresponding to the first opening and a fourth opening corresponding to the second opening in the substrate. The third opening includes a second inclined sidewall. A conductive layer is formed on the substrate. The conductive layer fills the third opening and the fourth opening. A portion of the conductive layer is removed by using the conductive layer located in the third opening as a stop layer to form a mark in the third opening and a TSV in the fourth opening.

Claims (30)

1 . A manufacturing method of a semiconductor structure, comprising:

providing a substrate;

forming a patterned photoresist layer on the substrate by a lithography process, wherein the patterned photoresist layer comprises a first opening and a second opening, and the first opening comprises a first inclined sidewall;

performing an etching process on the substrate by using the patterned photoresist layer as a mask to form a third opening corresponding to the first opening and a fourth opening corresponding to the second opening in the substrate, wherein the third opening comprises a second inclined sidewall;

forming a conductive layer on the substrate, wherein the conductive layer fills the third opening and the fourth opening; and

removing a portion of the conductive layer by using the conductive layer located in the third opening as a stop layer to form a mark in the third opening and a through-substrate via in the fourth opening.

2 . The manufacturing method of the semiconductor structure according to claim 1 , wherein the conductive layer does not completely fill the third opening.

3 . The manufacturing method of the semiconductor structure according to claim 2 , wherein in the process of removing the portion of the conductive layer, a portion of the substrate is removed at the same time to remove a portion of the third opening that is not completely filled.

4 . The manufacturing method of the semiconductor structure according to claim 3 , wherein a method of removing the portion of the conductive layer and the portion of the substrate comprises a chemical mechanical polishing method.

5 . The manufacturing method of the semiconductor structure according to claim 1 , wherein a width of the first opening is smaller than a width of the second opening, and a width of the third opening is smaller than a width of the fourth opening.

6 . The manufacturing method of the semiconductor structure according to claim 1 , wherein a width of a top portion of the first opening is greater than a width of a bottom portion of the first opening.

7 . The manufacturing method of the semiconductor structure according to claim 1 , wherein a cross-sectional shape of the first opening comprises a funnel shape.

8 . The manufacturing method of the semiconductor structure according to claim 1 , wherein a width of a top portion of the third opening is greater than a width of a bottom portion of the third opening.

9 . The manufacturing method of the semiconductor structure according to claim 1 , wherein a cross-sectional shape of the third opening comprises a funnel shape.

10 . The manufacturing method of the semiconductor structure according to claim 1 , wherein the patterned photoresist layer is consumed and removed in the etching process.

11 . The manufacturing method of the semiconductor structure according to claim 1 , wherein the lithography process comprises:

forming a photoresist layer on the substrate;

performing an exposure process on the photoresist layer by using a photomask as a mask; and

performing a development process on the photoresist layer to form the patterned photoresist layer after performing the exposure process.

12 . The manufacturing method of the semiconductor structure according to claim 11 , wherein a method of forming the photoresist layer comprises a spin coating method.

13 . The manufacturing method of the semiconductor structure according to claim 11 , wherein the photomask comprises:

a transparent substrate; and

a light-shielding layer located on the transparent substrate, wherein the light-shielding layer comprises a fifth opening and a sixth opening, the first opening corresponds to the fifth opening, and the second opening corresponds to the sixth opening.

14 . The manufacturing method of the semiconductor structure according to claim 13 , wherein the photomask comprises gray-tone regions, and the gray-tone regions are located in the fifth opening and are adjacent to sidewalls of the fifth opening.

15 . The manufacturing method of the semiconductor structure according to claim 14 , wherein a light transmittance of the gray-tone regions is greater than 0% and less than 100%.

16 . The manufacturing method of the semiconductor structure according to claim 14 , wherein the light transmittance of the gray-tone region is increased in a direction away from the sidewall of the fifth opening.

17 . The manufacturing method of the semiconductor structure according to claim 14 , wherein the light-shielding layer comprises island-shape patterns, and the island-shape patterns are located in the gray-tone regions and are separated from each other.

18 . The manufacturing method of the semiconductor structure according to claim 13 , wherein there is no gray-tone region in the sixth opening.

19 . The manufacturing method of the semiconductor structure according to claim 13 , wherein a material of the transparent substrate comprises quartz.

20 . The manufacturing method of the semiconductor structure according to claim 13 , wherein a material of the light-shielding layer comprises an opaque material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2024
From: LIN, HSIAO-CHIANG; NOMURA, YOSHIHIRO; HUANG, CHAO WEN
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 068907/0418 →
Priority Claims (1)
TW 113134643 · Sep 12, 2024 · national
Continuity (1)
Related Publication 20260076120A1 · Mar 12, 2026
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