NONVOLATILE MEMORY WITH MULTI-CELL WEIGHT STRUCTURE

1 . A nonvolatile storage apparatus, comprising:

nonvolatile memory cells;

bit lines connected to the nonvolatile memory cells; and

one or more control circuits connected to the nonvolatile memory cells and the bit lines, the one or more control circuits are configured to store weights in the nonvolatile memory cells, each individual weight stored by a group of two or more nonvolatile memory cells.

2 . The nonvolatile storage apparatus of claim 1 , wherein the one or more control circuits are configured to program each nonvolatile memory cell to three or more data states and an individual weight is represented by the combination of the states of at least a first nonvolatile memory cell and a second nonvolatile memory cell of the group.

3 . The nonvolatile storage apparatus of claim 2 , wherein the first nonvolatile memory cell is located in a first NAND string connected to a first bit line and the second nonvolatile memory cell is located in a second NAND string connected to a second bit line.

4 . The nonvolatile storage apparatus of claim 3 , wherein the one or more control circuits are further configured to add current through the first bit line and current through the second bit line to obtain a combined current in a vector-matrix multiplication operation.

5 . The nonvolatile storage apparatus of claim 2 , wherein the first nonvolatile memory cell is located in a first NAND string connected to a bit line and the second nonvolatile memory cell is located in a second NAND string connected to the bit line.

6 . The nonvolatile storage apparatus of claim 5 , wherein the one or more control circuits are configured to obtain a bit line current through the bit line as an output of a vector-matrix multiplication operation.

7 . The nonvolatile storage apparatus of claim 1 , wherein each nonvolatile memory cell is programmable to four data states, nonvolatile memory cells are configured as pairs of nonvolatile memory cells consisting of a first nonvolatile memory cell and a second nonvolatile memory cell, each individual weight stored by a combined data state of a pair of nonvolatile memory cells that is selected from seven combined data states.

8 . The nonvolatile storage apparatus of claim 7 , wherein each data state corresponds to a threshold voltage range and threshold voltage ranges of the four data states are unequally spaced apart.

9 . The nonvolatile storage apparatus of claim 1 , wherein the nonvolatile memory cells and the bit lines are located on a memory die and the one or more control circuits are located on a control die that is bonded to the memory die to form an integrated memory assembly.

10 . The nonvolatile storage apparatus of claim 1 , wherein the nonvolatile memory cells are arranged in vertical NAND strings in a 3D NAND memory structure and the bit lines extend across and connect to multiple vertical NAND strings.

11 . A method, comprising:

selecting a plurality of nonvolatile memory cells located in NAND strings;

programming the plurality of nonvolatile memory cells to data states that represent weights such that each weight is represented by combined data states of a group of two or more nonvolatile memory cells; and

performing a vector-matrix multiplication operation by obtaining combined current from groups of two or more nonvolatile memory cells.

12 . The method of claim 11 , further comprising applying select voltages on select gates corresponding to the plurality of nonvolatile memory cells to provide an input vector for the vector-matrix multiplication operation.

13 . The method of claim 12 , further comprising applying read voltages on selected word lines coupled to the NAND strings and applying pass voltages on non-selected word lines coupled to the NAND strings to select the plurality of nonvolatile memory cells for vector-matrix multiplication.

14 . The method of claim 11 , further comprising adding at least a first current from a first bit line and a second current from a second bit line to obtain a combined current for a group of two or more nonvolatile memory cells.

15 . The method of claim 11 , further comprising measuring current through a bit line while a group of two or more NAND strings that are connected to the bit line and that contain the two or more nonvolatile memory cells of the group are selected to obtain a combined current for the group of two or more nonvolatile memory cells.

16 . The method of claim 15 , further comprising applying read voltages to selected word lines coupled to the group of two or more nonvolatile memory cells while applying pass voltages to unselected word lines coupled to other nonvolatile memory cells in the group of two or more NAND strings to obtain the combined current.

17 . The method of claim 11 , wherein each group consists of a first nonvolatile memory cell and a second nonvolatile memory cell and the programming includes programming the first nonvolatile memory cell to a first data state selected from four data states, programming the second nonvolatile memory cell to a second data state selected from the four data states, the combined first and second data states representing a combined data state from seven combined data states.

18 . The method of claim 17 , further comprising:

determining for each weight to be programmed a first data state to program the first nonvolatile memory cell and a second data state to program the second nonvolatile memory cell.

19 . A memory system, comprising:

a three dimensional NAND memory structure having bit lines and nonvolatile memory cells connected in series to form NAND strings connected to the bit lines; and

means for storing weights in the nonvolatile memory cells, each individual weight stored by a combination of data states of two or more nonvolatile memory cells.

20 . The memory system of claim 19 , wherein the three dimensional NAND memory structure is located on a memory die and the means for storing weights is located on a control die that is bonded to the memory die to form an integrated memory assembly.