Granted Patent B2

US 12,650,785 · App. 18/944,310 · Granted Jun 9, 2026

Inventors: Jiayue Shi (Guangdong, CN); Jiajun Xu (Guangdong, CN)

Assignee: VIVO MOBILE COMMUNICATION CO., LTD.

G06F3/0655G06F3/0604G06F3/0679

Abstract

Claims (76)

1 . A data transmission circuit, comprising a storage chip, a data transit chip, and a data processing chip, wherein

the storage chip, the data transit chip, and the data processing chip are sequentially connected in series;

the data transit chip is configured to read a first data packet with a first preset quantity of bits from the storage chip, process the first data packet into a plurality of second data packets each with a second preset quantity of bits, and send the second data packets to the data processing chip; and

a maximum quantity of bits of a data packet that the data processing chip is able to read at a time is a third preset quantity of bits, the second preset quantity of bits is less than or equal to the third preset quantity of bits, and the first preset quantity of bits is greater than the third preset quantity of bits;

wherein the data transit chip comprises a read module, a first cache module, a decoding module, a second cache module, and an encoding module, wherein

a first end of the read module is connected to the storage chip;

a second end of the read module, a first end of the first cache module, a second end of the first cache module, the decoding module, the second cache module, and a first end of the encoding module are sequentially connected in series; and

a second end of the encoding module is connected to the data processing chip, wherein

the read module reads the first data packet with the first preset quantity of bits from the storage chip and saves the first data packet in the first cache module, the decoding module decodes the first data packet cached in the first cache module and saves decoded data in the second cache module, and the encoding module processes, into the plurality of second data packets each with the second preset quantity of bits, data that is read from the second cache module;

wherein the data transmission circuit further comprises a display driver integrated circuit, wherein

the display driver integrated circuit comprises a first end, a second end, and a third end, and the first cache module further comprises a third end; and

the first end of the display driver integrated circuit is connected to the storage chip, the second end of the display driver integrated circuit is connected to the first end of the read module, and the third end of the display driver integrated circuit is connected to the third end of the first cache module;

wherein the data transit chip is a frame interpolation chip, and the read module is configured to send a data reading instruction to the display driver integrated circuit causing the display driver integrated circuit to read the first data packet with the first preset quantity of bits from the storage chip according to the data reading instruction, and saving the first data packet in the first cache module.

2 . The data transmission circuit according to claim 1 , wherein the encoding module comprises an encoding unit and an editing unit, wherein

the encoding module comprises a first end and a second end, and the editing unit comprises a first end and a second end;

the first end of the encoding unit is connected to the second cache module, and the second end of the encoding unit is connected to the first end of the editing unit; and

the second end of the editing unit is connected to the data processing chip.

3 . The data transmission circuit according to claim 1 , wherein the data processing chip comprises a third cache module and a memory module, wherein

the third cache module comprises a first end and a second end, the first end of the third cache module is connected to the encoding module, and the second end of the third cache module is connected to the memory module.

4 . A data transmission method, applied to a data transmission circuit, wherein the data transmission circuit comprises: a storage chip, a data transit chip, and a data processing chip, wherein

the storage chip, the data transit chip, and the data processing chip are sequentially connected in series;

the data transit chip is configured to read a first data packet with a first preset quantity of bits from the storage chip, process the first data packet into a plurality of second data packets each with a second preset quantity of bits, and send the second data packets to the data processing chip; and

a maximum quantity of bits of a data packet that the data processing chip is able to read at a time is a third preset quantity of bits, the second preset quantity of bits is less than or equal to the third preset quantity of bits, and the first preset quantity of bits is greater than the third preset quantity of bits;

wherein the method comprises:

reading, by a data transit chip, a first data packet with a first preset quantity of bits from a storage chip;

processing, by the data transit chip, the first data packet into a plurality of second data packets each with a second preset quantity of bits; and

sending, by the data transit chip, the second data packets to a data processing chip, wherein

a maximum quantity of bits of a data packet that the data processing chip is able to read at a time is a third preset quantity of bits, the second preset quantity of bits is less than or equal to the third preset quantity of bits, and the first preset quantity of bits is greater than the third preset quantity of bits;

wherein the data transit chip comprises a read module, a first cache module, a decoding module, a second cache module, and an encoding module;

the reading, by a data transit chip, a first data packet with a first preset quantity of bits from a storage chip comprises:

reading, by the read module, the first data packet with the first preset quantity of bits from the storage chip, and saving the first data packet in the first cache module; and

the processing, by the data transit chip, the first data packet into a plurality of second data packets each with a second preset quantity of bits comprises:

decoding, by the decoding module, the first data packet cached in the first cache module, and saving decoded data in the second cache module; and

processing, by the encoding module into the plurality of second data packets each with the second preset quantity of bits, data that is read from the second cache module;

wherein the reading, by the read module, the first data packet with the first preset quantity of bits from the storage chip, and saving the first data packet in the first cache module comprises:

sending, by the read module, a data reading instruction to a display driver integrated circuit; and

reading, by the display driver integrated circuit, the first data packet with the first preset quantity of bits from the storage chip according to the data reading instruction, and saving the first data packet in the first cache module;

wherein the data transit chip is a frame interpolation chip.

5 . The method according to claim 4 , wherein the encoding module comprises an encoding unit and an editing unit; and

the encoding, by the encoding module into the plurality of second data packets each with the second preset quantity of bits, data that is read from the second cache module comprises:

encoding, by the encoding unit into the plurality of second data packets each with the second preset quantity of bits, the data that is read from the second cache module; and

generating, by the editing unit, a first verification code for any one of the second data packets based on the second data packet; and

for the any one of the second data packets, adding a start character to a packet header of the second data packet and sequentially adding the first verification code and an end character to a packet trailer of the second data packet, to update the second data packet, and sending the updated second data packet to the data processing chip.

6 . The method according to claim 4 , wherein the data transit chip comprises a read module, a first cache module, a decoding module, a second cache module, and an encoding module, wherein

a first end of the read module is connected to the storage chip;

a second end of the read module, a first end of the first cache module, a second end of the first cache module, the decoding module, the second cache module, and a first end of the encoding module are sequentially connected in series; and

a second end of the encoding module is connected to the data processing chip, wherein

the read module reads the first data packet with the first preset quantity of bits from the storage chip and saves the first data packet in the first cache module, the decoding module decodes the first data packet cached in the first cache module and saves decoded data in the second cache module, and the encoding module processes, into the plurality of second data packets each with the second preset quantity of bits, data that is read from the second cache module.

7 . The method according to claim 6 , wherein the data transmission circuit further comprises a display driver integrated circuit, wherein

the display driver integrated circuit comprises a first end, a second end, and a third end, and the first cache module further comprises a third end; and

the first end of the display driver integrated circuit is connected to the storage chip, the second end of the display driver integrated circuit is connected to the first end of the read module, and the third end of the display driver integrated circuit is connected to the third end of the first cache module.

8 . The method according to claim 6 , wherein the encoding module comprises an encoding unit and an editing unit, wherein

the encoding module comprises a first end and a second end, and the editing unit comprises a first end and a second end;

the first end of the encoding unit is connected to the second cache module, and the second end of the encoding unit is connected to the first end of the editing unit; and

the second end of the editing unit is connected to the data processing chip.

9 . The method according to claim 6 , wherein the data processing chip comprises a third cache module and a memory module, wherein

the third cache module comprises a first end and a second end, the first end of the third cache module is connected to the encoding module, and the second end of the third cache module is connected to the memory module.

10 . An electronic device, wherein the electronic device comprises a data transmission circuit, wherein the data transmission circuit comprises: a storage chip, a data transit chip, and a data processing chip, wherein

the storage chip, the data transit chip, and the data processing chip are sequentially connected in series;

the data transit chip is configured to read a first data packet with a first preset quantity of bits from the storage chip, process the first data packet into a plurality of second data packets each with a second preset quantity of bits, and send the second data packets to the data processing chip; and

a maximum quantity of bits of a data packet that the data processing chip is able to read at a time is a third preset quantity of bits, the second preset quantity of bits is less than or equal to the third preset quantity of bits, and the first preset quantity of bits is greater than the third preset quantity of bits;

wherein the data transit chip comprises a read module, a first cache module, a decoding module, a second cache module, and an encoding module, wherein

a first end of the read module is connected to the storage chip;

a second end of the read module, a first end of the first cache module, a second end of the first cache module, the decoding module, the second cache module, and a first end of the encoding module are sequentially connected in series; and

a second end of the encoding module is connected to the data processing chip, wherein

the read module reads the first data packet with the first preset quantity of bits from the storage chip and saves the first data packet in the first cache module, the decoding module decodes the first data packet cached in the first cache module and saves decoded data in the second cache module, and the encoding module processes, into the plurality of second data packets each with the second preset quantity of bits, data that is read from the second cache module;

wherein the data transmission circuit further comprises a display driver integrated circuit, wherein

the display driver integrated circuit comprises a first end, a second end, and a third end, and the first cache module further comprises a third end; and

the first end of the display driver integrated circuit is connected to the storage chip, the second end of the display driver integrated circuit is connected to the first end of the read module, and the third end of the display driver integrated circuit is connected to the third end of the first cache module;

wherein the data transit chip is a frame interpolation chip, and the read module is configured to send a data reading instruction to the display driver integrated circuit causing the display driver integrated circuit to read the first data packet with the first preset quantity of bits from the storage chip according to the data reading instruction, and saving the first data packet in the first cache module.

11 . The electronic device according to claim 10 , wherein the encoding module comprises an encoding unit and an editing unit, wherein

the encoding module comprises a first end and a second end, and the editing unit comprises a first end and a second end;

the first end of the encoding unit is connected to the second cache module, and the second end of the encoding unit is connected to the first end of the editing unit; and

the second end of the editing unit is connected to the data processing chip.

12 . The electronic device according to claim 10 , wherein the data processing chip comprises a third cache module and a memory module, wherein

the third cache module comprises a first end and a second end, the first end of the third cache module is connected to the encoding module, and the second end of the third cache module is connected to the memory module.

Assignments (1)

Priority Claims (1)

Continuity (2)

References Cited (22)