Pixel and display device including the same
Disclosed is a pixel which includes a light emitting element, a first capacitor, a first transistor including a gate electrode connected to the first node, a second transistor including a gate electrode connected to a first scan line, a third transistor including a gate electrode connected to a second scan line, and a fourth transistor including a gate electrode connected to the second scan line. During a first initialization period, a first scan signal provided to the first scan line and a second scan signal provided to the second scan line are at an active level.
1 . A pixel comprising:
a light emitting element including a first electrode electrically connected to a first voltage line through which a first driving voltage is provided, a second electrode electrically connected to a second voltage line through which a second driving voltage whose voltage level is lower than a voltage level of the first driving voltage is provided;
a first capacitor connected between a first node and a second node;
a first transistor including a first electrode connected to a third node, a second electrode electrically connected to the first electrode of the light emitting element, and a gate electrode connected to the first node;
a second transistor including a first electrode connected to the first node, a second electrode connected to a third voltage line, and a gate electrode connected to a first scan line;
a third transistor including a first electrode connected to the first electrode of the light emitting element, a second electrode connected to a fifth voltage line, and a gate electrode connected to a second scan line;
a fourth transistor including a first electrode connected to a fourth voltage line, a second electrode connected to the third node, and a gate electrode connected to the second scan line;
a fifth transistor including a first electrode connected to the first voltage line, a second electrode connected to the third node, and a gate electrode connected to a third scan line;
a sixth transistor including a first electrode connected to the second electrode of the first transistor, a second electrode connected to the first node, and a gate electrode connected to the third scan line;
a seventh transistor including a first electrode connected to the sixth voltage line through which a reference voltage is provided, a second electrode connected to the second node, and a gate electrode connected to the third scan line; and
an eighth transistor including a first electrode connected to a data line, a second electrode connected to the second node, and a gate electrode connected to a fourth scan line,
wherein, during a first initialization period, a first scan signal provided to the first scan line and a second scan signal provided to the second scan line are at an active level, and
wherein, during the first initialization period, a bias voltage is provided from the fourth voltage line to the third node.
2 . The pixel of claim 1 , wherein, in the first initialization period, a width of a second activation period of the second scan signal is narrower than a width of a first activation period of the first scan signal.
3 . The pixel of claim 1 , wherein, during the first initialization period, a first initialization voltage is provided from the third voltage line to the first node.
4 . The pixel of claim 1 , wherein, during the first initialization period, a second initialization voltage is provided from the fifth voltage line to the first electrode of the light emitting element.
5 . The pixel of claim 1 , wherein each of the second transistor and the sixth transistor includes a plurality of transistors connected in series.
6 . The pixel of claim 1 , further comprising:
a ninth transistor including a first electrode connected to the first voltage line, a second electrode connected to the third node, and a gate electrode connected to an emission line; and
a tenth transistor including a first electrode connected to the second electrode of the first transistor, a second electrode connected to the first electrode of the light emitting element, and a gate electrode connected to the emission line.
7 . The pixel of claim 6 , wherein, during a compensation period, a third scan signal provided to the third scan line is at the active level, and the first driving voltage is provided to the first node through the fifth transistor, the first transistor, and the sixth transistor.
8 . The pixel of claim 7 , wherein the first initialization period and the compensation period are alternately repeated plural times.
9 . The pixel of claim 8 , wherein a plurality of first initialization periods include a (1-1)-th initialization period and a (1-2)-th initialization period provided following the (1-1)-th initialization period,
wherein, during the (1-1)-th initialization period, the bias voltage has a first voltage level, and
wherein, during the (1-2)-th initialization period, the bias voltage has a second voltage level higher than the first voltage level.
10 . The pixel of claim 7 , wherein, during a second initialization period, the first scan signal is at the active level.
11 . The pixel of claim 10 , wherein the compensation period is disposed between the first initialization period and the second initialization period.
12 . The pixel of claim 7 , wherein, during a data write period provided following the first initialization period and the compensation period, a fourth scan signal provided to the fourth scan line is at the active level.
13 . The pixel of claim 12 , wherein, during a bias period provided following the data write period, the second scan signal is at the active level.
14 . The pixel of claim 13 , wherein, during an emission period provided following the bias period, an emission signal provided to the emission line is at the active level, and
wherein, during the emission period, the light emitting element emits a light.
15 . A display device comprising:
a display panel including a pixel connected to a plurality of scan lines, an emission line, and a data line;
a driving circuit configured to drive the plurality of scan lines and the emission line in response to a scan control signal;
a driving controller configured to output the scan control signal; and
a voltage generator configured to generate a plurality of driving voltages,
wherein the pixel includes:
a light emitting element including a first electrode electrically connected to a first voltage line through which a first driving voltage is provided, a second electrode electrically connected to a second voltage line through which a second driving voltage whose voltage level is lower than a voltage level of the first driving voltage is provided;
a first capacitor connected between a first node and a second node;
a first transistor including a first electrode connected to a third node, a second electrode electrically connected to the first electrode of the light emitting element, and a gate electrode connected to the first node;
a second transistor including a first electrode connected to the first node, a second electrode connected to a third voltage line through which a first initialization voltage is provided, and a gate electrode connected to a first scan line;
a third transistor including a first electrode connected to the first electrode of the light emitting element, a second electrode connected to a fifth voltage line through which a second initialization voltage is provided, and a gate electrode connected to a second scan line;
a fourth transistor including a first electrode connected to a fourth voltage line, a second electrode connected to the third node, and a gate electrode connected to the second scan line;
a fifth transistor including a first electrode connected to the first voltage line, a second electrode connected to the third node, and a gate electrode connected to a third scan line;
a sixth transistor including a first electrode connected to the second electrode of the first transistor, a second electrode connected to the first node, and a gate electrode connected to the third scan line;
a seventh transistor including a first electrode connected to a sixth voltage line through which a reference voltage is provided, a second electrode connected to the second node, and a gate electrode connected to the third scan line; and
an eighth transistor including a first electrode connected to the data line, a second electrode connected to the second node, and a gate electrode connected to a fourth scan line,
wherein, during a first initialization period, a first scan signal provided to the first scan line and a second scan signal provided to the second scan line are at an active level, and
wherein, during the first initialization period, a bias voltage is provided from the fourth voltage line to the third node.
16 . The display device of claim 15 , wherein, during the first initialization period,
a first initialization voltage is provided from the third voltage line to the first node, and
a second initialization voltage is provided from the fifth voltage line to the first electrode of the light emitting element.
17 . The display device of claim 15 , wherein each of the second transistor and the sixth transistor includes a plurality of transistors connected in series.
18 . The display device of claim 16 , wherein the pixel further includes:
a ninth transistor including a first electrode connected to the first voltage line, a second electrode connected to the third node, and a gate electrode connected to the emission line; and
a tenth transistor including a first electrode connected to the second electrode of the first transistor, a second electrode connected to the first electrode of the light emitting element, and a gate electrode connected to the emission line.
19 . The display device of claim 18 , wherein, during a compensation period, a third scan signal provided to the third scan line is at the active level, and the first driving voltage is provided to the first node through the fifth transistor, the first transistor, and the sixth transistor.
20 . The display device of claim 19 , wherein the first initialization period and the compensation period are alternately repeated plural times,
wherein a plurality of first initialization periods include a (1-1)-th initialization period and a (1-2)-th initialization period provided following the (1-1)-th initialization period,
wherein, during the (1-1)-th initialization period, the bias voltage has a first voltage level, and
wherein, during the (1-2)-th initialization period, the bias voltage has a second voltage level higher than the first voltage level.
21 . An electronic device comprising the display device of claim 15 .