Granted Patent B2

US 12,730,488 · App. 18/951,922 · Granted Sep 8, 2026

Inventor: John-David Stuart Marsters (London, GB)

Assignee: Bank of America Corporation

G06F1/206G06F1/3296H03K19/20G06F1/3203G06F1/3287

Abstract

Claims (67)

1 . A reversible logic gate-based thermal management with software-controlled entropy offloading process with software-controlled thermal management in high-performance computing, comprising:

operating reversible logic gates in processor cores to preserve information during computations and minimize heat generation in high-computational intensity areas of the processor cores that exceed a predetermined activity threshold;

operating non-reversible logic gates in the processor cores in non-high-computational intensity areas of the processor cores that do not exceed the predetermined activity threshold;

monitoring real-time computational and temperature data in the processor cores using embedded thermal sensors and computational load monitors;

dynamically controlling the offloading of entropy from high-computation regions of the processor cores to a thermal output unit (TOU) via a software-based entropy offloading module, said module prioritizing the transfer of intermediate or unnecessary data from the high-computation areas;

offloading intermediate or unnecessary data from the processor cores to the TOU via a high-bandwidth memory channel, ensuring that excess entropy is efficiently transferred for further processing and heat dissipation;

performing irreversible computations in the TOU using layers of cascading non-reversible logic gates, each having more inputs than outputs, wherein the data is destroyed and heat is generated due to entropy conversion from information loss;

performing irreversible data destruction in the TOU and dissipating the heat generated through integrated heat dissipation mechanisms such as heat sinks and vapor chambers; and

adjusting offloading rates from the processor cores to the TOU and optimizing the performance of the reversible logic gates based on real-time thermal and computational data using a dynamic heat regulation module, thereby ensuring efficient thermal management and computational performance optimization.

2 . The process of claim 1 , wherein the reversible logic gates include Toffoli gates.

3 . The process of claim 1 , wherein the reversible logic gates include Fredkin gates.

4 . The process of claim 1 , wherein the reversible logic gates include both Toffoli gates and Fredkin gates.

5 . The process of claim 4 , wherein the thermal output unit (TOU) is internal to an integrated circuit on which the processor cores reside, and is coupled to a heat dissipation component, such as a heat sink or vapor chamber, to efficiently dissipate the heat generated by irreversible computations.

6 . The process of claim 5 , wherein the thermal output unit (TOU) is remote from the integrated circuit on which the processor cores reside, and is coupled to a heat dissipation component, ensuring that the heat generated by the irreversible computations in the TOU is dissipated away from the processing cores to maintain optimal thermal conditions.

7 . The process of claim 6 , wherein the thermal output unit (TOU) includes multi-level cascading logic gates, wherein each level reduces the number of outputs compared to the number of inputs, thereby progressively destroying information at each level of the TOU, resulting in more efficient entropy management and heat dissipation.

8 . The process of claim 7 , wherein the thermal output unit (TOU) further comprises a dynamic heat dissipation control module that adjusts the operation of heat dissipation mechanisms based on real-time thermal data collected from temperature sensors embedded within both the TOU and the processor cores, ensuring that heat is dissipated efficiently in response to variable workloads.

9 . The process of claim 8 , wherein the dynamic heat dissipation control module integrates with a liquid cooling system, wherein coolant circulates either through heat sinks external to the TOU processor package or through microchannels embedded in the TOU, providing additional heat dissipation for high-performance computational loads and preventing overheating in extreme computational conditions.

10 . The process of claim 9 , wherein the software-based entropy offloading module dynamically adjusts the rate of entropy offloading from the processor cores to the TOU based on the real-time temperature and computational load data, ensuring that data from high-computational areas is offloaded at optimal rates to prevent localized overheating in the cores.

11 . The process of claim 10 , further comprising a performance optimization module, which monitors the performance of both reversible and non-reversible logic gates in the processor cores, dynamically adjusting the balance of reversible gate operations based on computational intensity and thermal conditions to ensure that heat generation is minimized while maintaining high performance.

12 . The process of claim 11 , wherein the performance optimization module includes a predictive analytics component that uses machine learning algorithms to predict future thermal conditions based on historical computational data, allowing the system to proactively adjust the use of reversible and non-reversible logic gates before high thermal thresholds are reached.

13 . The process of claim 12 , wherein the system includes thermal imaging sensors within the processor package, which generate real-time thermal maps of the processor cores and TOU, allowing the system to visualize areas of high heat concentration and adjust entropy offloading and gate operations to mitigate thermal stress.

14 . The process of claim 13 , wherein the real-time thermal maps generated by the thermal imaging sensors are used to retrospectively analyze the performance of the reversible logic gates, enabling iterative design adjustments, including the selective replacement of non-reversible logic gates with reversible logic gates in high-computational intensity regions that exhibit excessive heat generation.

15 . The process of claim 14 , further comprising an iterative design refinement module that uses the thermal analysis data to refine the architecture of the processor over time, progressively improving thermal efficiency by increasing the proportion of reversible gates in regions prone to heat buildup, and optimizing the TOU's cascading logic gate structure to further enhance entropy offloading efficiency.

16 . The process of claim 15 , wherein the iterative design refinement module collaborates with the entropy offloading module to reallocate high-computation tasks to areas of the processor cores that have better thermal conditions, thereby optimizing overall system performance and ensuring balanced thermal loads across all cores.

17 . The process of claim 16 , wherein the processor cores are configured with region-specific optimization, wherein different regions within the cores have varying degrees of reversible and non-reversible gate configurations, each tailored to the specific computational tasks handled by that region to maximize efficiency and minimize heat generation.

18 . The process of claim 17 , wherein the thermal output unit (TOU) is capable of operating in both active and passive cooling modes, where passive cooling systems such as heat sinks and vapor chambers are engaged during lower computational loads, and active cooling systems such as fans and liquid cooling are additionally engaged during high-intensity workloads, ensuring adaptive and efficient thermal management based on real-time performance requirements.

19 . A reversible logic gate-based thermal management process with software-controlled entropy offloading and thermal management for high-performance computing, comprising:

operating reversible logic gates in processor cores, where said reversible logic gates are selectively activated in regions of high-computational intensity within the processor cores that exceed a predetermined activity threshold, the reversible gates preserving input-output state mappings during computations to prevent information loss, thereby reducing entropy conversion and minimizing heat generation in critical high-performance regions of the cores, enabling continuous high-speed operations without throttling due to excessive heat;

operating non-reversible logic gates in the processor cores in regions identified as non-high-computational intensity areas, wherein computational activity remains below the predetermined threshold, allowing irreversible computations to be conducted in these areas where heat generation is less of a concern, thus optimizing overall processing efficiency while controlling heat generation across the processor cores;

monitoring real-time computational load and temperature data within the processor cores using embedded thermal sensors and computational load monitors, the data being collected by a software-based entropy offloading module, said module continuously analyzing and evaluating the thermal conditions and computational intensity of each core to detect regions where computational intensity is generating excessive heat, and dynamically adjusting system performance and heat management parameters accordingly;

dynamically controlling the offloading of entropy from high-computational regions of the processor cores to a thermal output unit (TOU) via the software-based entropy offloading module, wherein the module prioritizes the identification and transfer of intermediate or unnecessary data from regions of the processor cores exceeding a predefined computational threshold, offloading the data to prevent localized heat accumulation and thermal stress within the cores;

offloading intermediate or unnecessary data from the processor cores to the TOU through high-bandwidth memory channels, wherein the data is transferred in real-time to prevent delays in offloading and to optimize the removal of entropy-generating data from the cores, ensuring that the processing resources of the cores are devoted to high-priority computational tasks, while offloading surplus data to the TOU for irreversible processing;

performing irreversible computations in the TOU using a cascading arrangement of multi-input to reduced-output non-reversible logic gates, wherein each level of non-reversible logic gates in the TOU has more inputs than outputs, resulting in the progressive destruction of offloaded data and the generation of heat due to entropy conversion from information loss, with each stage in the cascade increasing the efficiency of entropy destruction and minimizing the thermal load on the cores;

activating heat dissipation mechanisms within the TOU, said mechanisms comprising a combination of passive cooling systems, including heat sinks and vapor chambers, as well as active cooling systems such as liquid cooling loops and fans, designed to dissipate the heat generated by the irreversible computations performed within the TOU, ensuring that heat is managed in an isolated environment and preventing thermal feedback from impacting the performance of the processor cores;

adjusting offloading rates of entropy from the processor cores to the TOU based on real-time feedback from a thermal management module, wherein the thermal management module continuously monitors temperature data collected from sensors embedded in both the processor cores and the TOU, dynamically optimizing the rate of entropy offloading to ensure that heat does not accumulate in the cores or the TOU, and that the system operates within safe thermal thresholds, even during periods of high computational demand;

regulating the performance of the reversible logic gates within the processor cores through a performance optimization module, wherein the module dynamically adjusts the activation and deactivation of the reversible logic gates based on computational intensity and thermal data in real-time, prioritizing the use of reversible logic gates in regions where computational loads exceed the predefined threshold and heat generation is a concern, while deactivating reversible gates in lower-load areas to optimize power consumption and maintain efficient system performance;

configuring the TOU to be either internal or remote from the integrated circuit (IC) containing the processor cores, wherein when the TOU is internal, it is thermally coupled to a heat dissipation component such as heat sinks or vapor chambers to manage localized heat production, and when the TOU is remote, it is connected to a separate, external heat dissipation system to handle heat dissipation at a distance from the cores, ensuring that the thermal effects of entropy destruction are isolated and do not interfere with core performance;

integrating a dynamic heat regulation module that adjusts both the entropy offloading rates to the TOU and the operational performance of the reversible logic gates, said adjustments being made based on continuous real-time analysis of temperature data from the thermal management module, ensuring that heat buildup is prevented in both the processor cores and the TOU, and optimizing the performance of the overall system for sustained high-computation tasks;

utilizing multi-level cascading logic gates within the TOU, wherein each subsequent level of logic gates processes the output of the previous level, progressively reducing the number of outputs compared to inputs, thereby efficiently destroying information while generating and isolating heat, ensuring that entropy is managed in a controlled and structured manner to prevent excessive heat accumulation;

employing predictive analytics within the performance optimization module, wherein the system leverages historical computational and thermal data to predict future thermal conditions, allowing proactive adjustments to entropy offloading rates and reversible gate usage before thermal thresholds are reached, thereby preventing performance degradation due to overheating;

integrating real-time thermal imaging sensors within the processor cores and the TOU, wherein the thermal imaging sensors generate detailed thermal maps that visualize regions of high computational intensity and heat generation, said maps being used to adjust the operations of the reversible and non-reversible logic gates, as well as entropy offloading rates, in real-time to balance the thermal load across the system;

retrofitting high-entropy regions of the processor cores identified through thermal imaging with additional reversible logic gates, wherein standard non-reversible logic gates in these areas are selectively replaced with reversible logic gates to minimize entropy conversion and heat generation, the retrofitted regions being optimized for efficient thermal management, with offloaded data from these regions being transferred to the TOU for irreversible computation;

iteratively refining the design of the system through an iterative design refinement module, wherein the module uses data from thermal imaging and real-time performance monitoring to continuously adjust the architecture of the processor cores and TOU, including increasing the proportion of reversible gates in high-computational regions, optimizing the cascading logic gate structures in the TOU, and refining the entropy offloading mechanisms to improve the thermal efficiency of the system over time;

adjusting the balance of computational tasks across the processor cores based on region-specific optimization, wherein different regions of the cores are configured with varying concentrations of reversible and non-reversible logic gates depending on the specific computational and thermal requirements of the tasks being handled, enabling optimal heat management and computational efficiency in each region; and

allowing the TOU to operate in both active and passive cooling modes, wherein passive heat dissipation systems such as heat sinks and vapor chambers manage heat during lower computational loads, while active cooling systems such as liquid cooling and fans are activated during periods of high-computational intensity, providing adaptive thermal management that scales according to real-time system requirements,

wherein the system is capable of scaling to handle increasing levels of high-performance computing tasks, including the addition of processor cores, TOUs, and enhanced cooling systems to accommodate growing computational and thermal demands, ensuring that the system maintains optimal performance levels under varying workloads while preventing overheating, minimizing thermal throttling, and reducing overall energy consumption, enabling the system to support applications in artificial intelligence, machine learning, real-time data processing, and other high-performance environments.

20 . A reversible logic gate-based thermal management system with software-controlled entropy offloading and thermal management for high-performance computing, comprising:

processor cores, each configured to execute high-computational intensity tasks, the processor cores comprising reversible logic gates and non-reversible logic gates, wherein the reversible logic gates are selectively activated in regions of the processor cores that exceed a predetermined computational activity threshold, preserving input-output state mappings during computations to prevent information loss, thus minimizing entropy conversion and heat generation, and the non-reversible logic gates are deployed in regions where computational intensity is below the threshold, allowing irreversible computations to proceed where heat generation is less critical;

reversible logic gates, embedded within the processor cores, configured to prevent irreversible information loss during computations in high-intensity regions, thereby reducing heat generation through minimized entropy conversion, and dynamically controlled based on real-time computational intensity and thermal conditions;

non-reversible logic gates, embedded within the processor cores, configured to handle computations in regions of the cores where activity does not exceed the predetermined threshold, allowing standard irreversible operations that produce more heat but are limited to lower-intensity areas, thereby optimizing the thermal balance across the processor cores;

entropy offloading module, configured to dynamically monitor real-time computational loads and temperature data from embedded sensors in the processor cores, the module being responsible for detecting high-computation regions that exceed a predefined activity threshold and initiating the offloading of intermediate or unnecessary data from these regions to a thermal output unit (TOU) for controlled destruction and heat entropy management, based on the detected intensity and thermal conditions;

thermal output unit (TOU), structurally separate from the processor cores and connected to them via high-bandwidth memory channels, the TOU being configured to receive offloaded data and perform irreversible computations using a cascading arrangement of multi-input to reduced-output non-reversible logic gates, wherein each level of the cascading logic gates has more inputs than outputs, progressively destroying information and generating heat through entropy conversion, while isolating the heat generation from the processor cores;

high-bandwidth memory channels, connecting the processor cores to the TOU, enabling the real-time transfer of unwanted information from reversible gates in high-computational regions to the TOU for irreversible processing, thereby preventing thermal overload in the processor cores and ensuring efficient offloading of entropy during intense computational tasks;

thermal management module, configured to continuously monitor real-time temperature data from sensors embedded within both the processor cores and the TOU, said module dynamically adjusting the rates of entropy offloading to the TOU, based on detected thermal conditions, to ensure that heat generation in the processor cores remains below critical thresholds, while preventing heat buildup in the TOU by optimizing the timing and rate of irreversible computations;

heat dissipation mechanisms, integrated into the TOU and comprising both passive cooling systems, such as heat sinks and vapor chambers, and active cooling systems, including liquid cooling loops and fans, the dissipation mechanisms being designed to manage the heat generated by irreversible computations within the TOU, isolating the thermal effects from the processor cores and ensuring that the TOU operates at an optimal temperature, regardless of the computational load;

performance optimization module, configured to regulate the operation of the reversible logic gates within the processor cores, the module dynamically adjusting the activation and deactivation of the reversible logic gates based on real-time computational intensity and thermal data, prioritizing the use of reversible logic gates in high-computational intensity regions to reduce heat generation, while deactivating reversible gates in lower-load regions to optimize energy efficiency and computational performance;

predictive analytics component, integrated within the performance optimization module, wherein machine learning algorithms are used to analyze historical computational and temperature data to predict future thermal conditions, allowing the system to proactively adjust entropy offloading rates and reversible gate usage before high thermal thresholds are reached, thereby preventing heat-induced performance degradation and optimizing system efficiency;

thermal imaging subsystem, comprising real-time thermal imaging sensors embedded within both the processor cores and the TOU, the sensors generating detailed thermal maps of the cores to visualize regions of high computational intensity and heat generation, wherein the thermal maps are used to dynamically adjust entropy offloading rates, reversible gate usage, and non-reversible computations in response to the real-time thermal data, ensuring that the system maintains optimal thermal balance across all regions of the processor cores and TOU;

retrofitting mechanism, configured to selectively replace non-reversible logic gates in high-entropy regions of the processor cores with additional reversible logic gates, based on the thermal maps generated by the thermal imaging subsystem, wherein the retrofitting mechanism is used to reduce heat generation in critical regions by transforming them into thermally optimized zones with minimal entropy conversion, and offloading data from these retrofitted regions to the TOU for irreversible computation;

cascading non-reversible logic gates, embedded within the TOU and arranged in a multi-level configuration, wherein each level progressively reduces the number of outputs compared to inputs, efficiently destroying offloaded data and generating heat in a controlled manner, the cascading gates ensuring that entropy is managed efficiently within the TOU, preventing excessive heat generation while isolating the thermal effects from the processor cores;

iterative design refinement module, integrated with the thermal management and performance optimization modules, the design refinement module using data from thermal imaging, real-time performance monitoring, and predictive analytics to continually adjust the architecture of the processor cores and TOU, including increasing the concentration of reversible gates in high-computational regions, refining the cascading gate structures in the TOU, and optimizing entropy offloading pathways to further improve thermal efficiency and system performance over time;

a dynamic heat regulation module, responsible for adjusting both the offloading rates of data from the processor cores to the TOU and the performance of the reversible logic gates, said module dynamically analyzing real-time thermal data from sensors embedded across the system and regulating heat dissipation mechanisms within the TOU to maintain optimal operating temperatures, preventing overheating in both the processor cores and the TOU during periods of high computational demand;

region-specific optimization architecture, wherein different regions of the processor cores are configured with varying concentrations of reversible and non-reversible logic gates, the configuration being tailored to the specific computational tasks handled by each region to ensure optimal thermal management and computational efficiency, with high-computation regions being prioritized for reversible gate operation to minimize heat generation;

cooling components, comprising both active and passive cooling systems, integrated into the system architecture to manage the heat generated by both the processor cores and the TOU, wherein passive cooling systems such as heat sinks and vapor chambers are used to dissipate heat during low and moderate computational loads, while active cooling systems such as liquid cooling loops and fans are additionally activated during periods of high computational intensity to provide additional thermal management, ensuring that the system maintains safe operating temperatures under all workload conditions;

a system control module, responsible for coordinating the overall thermal management process, including the operation of reversible and non-reversible logic gates, entropy offloading to the TOU, heat dissipation mechanisms, and performance optimization, wherein the control module interfaces with all subsystems to ensure seamless coordination between computational tasks, heat management, and real-time monitoring of thermal conditions; and

a processor scalability structure, enabling the system to scale for different high-performance computing tasks, wherein additional processor cores, TOUs, and cooling systems can be added to meet growing computational and thermal demands while maintaining the same entropy offloading, thermal management, and performance optimization processes, thereby ensuring that the system can handle increasing workloads without compromising performance or overheating,

wherein the system is capable of sustaining high-performance computing tasks by dynamically managing entropy conversion and heat generation within the processor cores and TOU, enabling the system to operate at higher clock speeds and processing rates without the risk of thermal throttling, overheating, or performance degradation, while reducing overall energy consumption through the efficient use of reversible logic gates, predictive analytics, and adaptive cooling strategies, making the system suitable for applications in artificial intelligence, machine learning, real-time data processing, and other demanding computing environments.

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References Cited (32)