Structure for an apparatus for monitoring and controlling heat generation in a multi-core processor
View Patent ↗A design structure for a processor may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may control heat generation in a multi-core processor. The design structure may specify that each processor core includes a temperature sensor that reports temperature information to a processor controller. The design structure may also specify that if a particular processor core exceeds a predetermined temperature, the processor controller disables that processor core to allow that processor core to cool. The design structure may also specify that the processor controller enables the previously disabled processor core when the previously disabled processor core cools sufficiently to a normal operating temperature. In this manner, a multi-core processor may avoid undesirable hot spots that impact processor life.
1. A design structure embodied in a nontransitory machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a plurality of processor cores situated on a semiconductor die, each processor core including a respective temperature sensor that senses the temperature thereof; and
a core power controller, coupled to the plurality of processor cores, situated on the semiconductor die, the core power controller being capable of receiving temperature information from each processor core, the core power controller disabling the processor cores whose temperatures exceed a first predetermined temperature value, the core power controller disabling first selected processor cores during a first power control time interval while other processor cores remain enabled, the core power controller disabling second selected processor cores during a second power control time interval following the first power control time interval, the second selected processor cores of the second power control time interval being different from the first selected processor cores of the first power control time interval, the core power controller disabling other selected processor cores during successive power control time intervals that follow the second time power control interval to form a complete cycle wherein all processor cores have been disabled once.
2. The design structure of claim 1 , wherein the core power controller disables a selected core by one of powering off the selected core and clock gating the selected core.
3. The design structure of claim 1 , wherein the core power controller enables a previously disabled processor core when the previously disabled processor core cools to a temperature less than the a second predetermined temperature value, the second predetermined temperature value being less than the first predetermined temperature value.
4. The design structure of claim 1 , wherein the core power controller transfers a job from a first processor core that will subsequently become disabled to a second processor core that is enabled prior to disabling the first processor core.
5. The design structure of claim 1 , further comprising:
a first clock circuit, coupled to a selected processor core, configured to clock the selected processor core at a first frequency;
a second clock circuit, coupled to the selected processor core, configured to clock the selected processor core at a second frequency greater than the first frequency for burst mode operation;
the core power controller being configured to cause the second clock circuit to clock the selected processor core at the second frequency for burst mode operation, the core power controller disabling the selected processor core if the temperature of the selected processor core exceeds the first predetermined temperature value.
6. A hardware description language (HDL) design structure encoded on a non-transitory machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a processor, wherein said HDL design structure comprises:
a first element processed to generate a functional computer-simulated representation of a plurality of processor cores situated on a semiconductor die, each processor core including a respective temperature sensor that senses the temperature thereof; and
a second element processed to generate a functional computer-simulated representation of a core power controller, coupled to the plurality of processor cores, situated on the semiconductor die, the core power controller being capable of receiving temperature information from each processor core, the core power controller disabling the processor cores whose temperatures exceed a first predetermined temperature value, the core power controller disabling first selected processor cores during a first power control time interval while other processor cores remain enabled, the core power controller disabling second selected processor cores during a second power control time interval following the first power control time interval, the second selected processor cores of the second power control time interval being different from the first selected processor cores of the first power control time interval, the core power controller disabling other selected processor cores during successive power control time intervals that follow the second time power control interval to form a complete cycle wherein all processor cores have been disabled once.
7. The HDL design structure of claim 6 , wherein the core power controller disables a selected core by one of powering off the selected core and clock gating the selected core.
8. The HDL design structure of claim 6 , wherein the core power controller enables a previously disabled processor core when the previously disabled processor core cools to a temperature less than the a second predetermined temperature value, the second predetermined temperature value being less than the first predetermined temperature value.
9. The HDL design structure of claim 6 , wherein the core power controller transfers a job from a first processor core that will subsequently become disabled to a second processor core that is enabled prior to disabling the first processor core.
10. The HDL design structure of claim 6 , further comprising:
a first clock circuit, coupled to a selected processor core, configured to clock the selected processor core at a first frequency;
a second clock circuit, coupled to the selected processor core, configured to clock the selected processor core at a second frequency greater than the first frequency for burst mode operation;
the core power controller being configured to cause the second clock circuit to clock the selected processor core at the second frequency for burst mode operation, the core power controller disabling the selected processor core if the temperature of the selected processor core exceeds the first predetermined temperature value.
11. A method in a computer-aided design system for generating a functional design model of a processor, the method comprising:
generating a functional computer-simulated representation of a plurality of processor cores situated on a semiconductor die, each processor core including a respective temperature sensor that senses the temperature thereof; and
generating a functional computer-simulated representation of a core power controller, coupled to the plurality of processor cores, situated on the semiconductor die, the core power controller being capable of receiving temperature information from each processor core, the core power controller disabling the processor cores whose temperatures exceed a first predetermined temperature value, the core power controller disabling first selected processor cores during a first power control time interval while other processor cores remain enabled, the core power controller disabling second selected processor cores during a second power control time interval following the first power control time interval, the second selected processor cores of the second power control time interval being different from the first selected processor cores of the first power control time interval, the core power controller disabling other selected processor cores during successive power control time intervals that follow the second time power control interval to form a complete cycle wherein all processor cores have been disabled once.
12. The method of claim 11 , wherein the core power controller disables a selected core by one of powering off the selected core and clock gating the selected core.
13. The method of claim 11 , wherein the core power controller enables a previously disabled processor core when the previously disabled processor core to a temperature less than the a second predetermined temperature value, the second predetermined temperature value being less than the first predetermined temperature value.
14. The method of claim 11 , wherein the core power controller transfers a job from a first processor core that will subsequently become disabled to a second processor core that is enabled prior to disabling the first processor core.
15. The method of claim 11 , further comprising:
generating a functional computer-simulated representation of a first clock circuit, coupled to a selected processor core, configured to clock the selected processor core at a first frequency;
generating a functional computer-simulated representation of a second clock circuit, coupled to the selected processor core, configured to clock the selected processor core at a second frequency greater than the first frequency for burst mode operation;
the core power controller being configured to cause the second clock circuit to clock the selected processor core at the second frequency for burst mode operation, the core power controller disabling the selected processor core if the temperature of the selected processor core exceeds the first predetermined temperature value.