IP Library › Patent Application 18952852
Patent Application
App. No. 18/952,852

INTEGRATED COOLING ASSEMBLIES FOR ADVANCED DEVICE PACKAGING AND METHODS OF MANUFACTURING THE SAME

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Quick Facts
Patent No.
US None
App. No.
18/952,852
Abstract

A device package comprising an integrated cooling assembly. The integrated cooling assembly comprises a semiconductor device and a cold plate attached to the semiconductor device. The cold plate comprises a top portion and a bottom portion horizontally adjacent to the top portion. The top portion comprises upper cavity dividers extending downwardly to define upper cavity volumes. The bottom portion comprises lower cavity dividers extending upwardly to define lower cavity volumes. The upper cavity dividers and the lower cavity dividers alternate across a horizontal length of the cold plate.

Claims (47)

1 . (canceled)

2 . A device package comprising:

an integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device by direct dielectric bonds, wherein:

the cold plate comprises a top portion and a bottom portion vertically adjacent to the top portion;

the top portion comprises upper cavity dividers extending downwardly to define upper cavity volumes;

the bottom portion comprises lower cavity dividers extending upwardly to define lower cavity volumes; and

the upper cavity dividers and the lower cavity dividers are disposed across a horizontal length of the cold plate with a lateral spacing between adjacent upper and lower cavity dividers.

3 . The device package of claim 2 , wherein:

the upper cavity dividers are spaced horizontally across the top portion at a first lateral spacing and the lower cavity dividers are spaced horizontally across the bottom portion at a second lateral spacing different to the first lateral spacing; and

the lateral spacings between the cavity dividers are greater than a horizontal width of the cavity dividers.

4 . The device package of claim 2 , wherein:

the top portion comprises an upper surface attached to an upper sidewall, the upper sidewall extending downwardly from the upper surface.

5 . The device package of claim 4 , wherein the upper cavity dividers extend downwardly from the upper surface to substantially a same depth as a depth of the upper sidewall.

6 . The device package of claim 4 , wherein the upper cavity dividers extend between opposite sides of the upper sidewall to define the upper cavity volumes.

7 . The device package of claim 2 , wherein:

the bottom portion comprises a lower surface attached to a lower sidewall, the lower sidewall extending upwardly from the lower surface; and

the lower surface is attached to a backside of the semiconductor device.

8 . The device package of claim 7 , wherein the lower cavity dividers extend upwardly from the lower surface to substantially a same depth as a depth of the lower sidewall.

9 . The device package of claim 2 , wherein:

the bottom portion comprises a lower sidewall extending upwardly from a backside of the semiconductor device; and

the lower cavity dividers are disposed on the backside of the semiconductor device.

10 . The device package of claim 9 , wherein the lower cavity dividers extend upwardly from the backside of the semiconductor device to substantially a same depth as a depth of the lower sidewall.

11 . The device package of claim 7 , wherein the lower cavity dividers extend between opposite sides of the lower sidewall to define the lower cavity volumes.

12 . The device package of claim 2 , wherein:

the top portion comprises an upper cavity separator attached between a pair of upper cavity dividers to define compartments within the upper cavity volumes, and

the bottom portion comprises a lower cavity separator attached between a pair of lower cavity dividers to define compartments within the lower cavity volumes.

13 . The device package of claim 2 , wherein surfaces of the upper cavity dividers slope towards the bottom portion at an angle greater than 90 degrees.

14 . The device package of claim 2 , wherein:

surfaces of the lower cavity dividers slope towards the top portion at an angle greater than 90 degrees; or

surfaces of the lower cavity dividers slope towards the top portion at an angle less than 90 degrees.

15 . The device package of claim 2 , wherein the upper cavity dividers are rows of first metal posts and the lower cavity dividers are rows of second metal posts.

16 . The device package of claim 2 , wherein the top portion of the cold plate comprises:

a package cover, the package cover having an inlet opening and an outlet opening disposed therethrough, and wherein:

the upper cavity volumes and the lower cavity volumes collectively define a coolant chamber volume therebetween; and

the coolant chamber volume is in fluid communication with the inlet opening and the outlet opening.

17 . The device package of claim 2 , wherein the integrated cooling assembly comprising plural semiconductor devices and the cold plate is attached to the plural semiconductor devices.

18 . The device package of claim 2 , wherein:

the upper cavity dividers define two longitudinal upper cavity volumes;

the lower cavity dividers define three longitudinal lower cavity volumes orthogonal to the longitudinal upper cavity volumes;

a first lower cavity volume overlaps with a first upper cavity volume only;

a second lower cavity volume overlaps with a second upper cavity volume only; and

a third lower cavity volume overlaps with both the first and the second upper cavity volumes.

19 . The device package of claim 2 , wherein the cold plate is attached to the semiconductor device by direct hybrid bonds.

20 . The device package of claim 2 , wherein:

the upper cavity volumes and the lower cavity volumes collectively define a coolant chamber volume therebetween; and

the device package further comprises upper and lower cavity separators to define a plurality of channels through the coolant chamber volume.

21 . The device package of claim 2 , wherein the upper cavity dividers and the lower cavity dividers alternate across a horizontal length of the cold plate.

Assignments (2)
SECURITY INTEREST Recorded May 28, 2025
From: ADEIA INC. (F/K/A XPERI HOLDING CORPORATION); ADEIA HOLDINGS INC.; ADEIA MEDIA HOLDINGS INC.; ADEIA IMAGING LLC; ADEIA MEDIA LLC; ADEIA MEDIA SOLUTIONS INC.; ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.; ADEIA TECHNOLOGIES INC.; ADEIA GUIDES INC.; ADEIA SOLUTIONS LLC; ADEIA SEMICONDUCTOR ADVANCED TECHNOLOGIES INC.; ADEIA SEMICONDUCTOR SOLUTIONS LLC; ADEIA SEMICONDUCTOR INTELLECTUAL PROPERTY LLC; ADEIA SEMICONDUCTOR TECHNOLOGIES LLC; ADEIA PUBLISHING INC.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 071454/0343 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2025
From: FOUNTAIN, GAIUS GILLMAN, JR.; HABA, BELGACEM; BANG, KYONG-MO
To: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Reel/Frame 069812/0319 →