IP Library Patent Application 18952911
Patent Application
App. No. 18/952,911

EMBEDDED COOLING ASSEMBLIES FOR ADVANCED DEVICE PACKAGING AND METHODS OF MANUFACTURING THE SAME

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Quick Facts
Patent No.
US None
App. No.
18/952,911
Abstract

A device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The package cover generally has an inlet opening and an outlet opening disposed there through. The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The device package may include a material layer between the package cover and the cold plate. The cold plate may include a patterned first side and an opposite second side. The patterned first side may include a base surface and sidewalls extending downward from the base surface, where the base surface is spaced apart from the semiconductor device to collectively define a coolant channel. Here, the coolant channel is in fluid communication with the inlet opening and the outlet opening through openings disposed through respective portions of the material layer.

Claims (47)

1 - 23 . (canceled)

24 . An integrated cooling assembly comprising:

a first semiconductor device;

a plurality of second semiconductor devices vertically arranged in a device stack; and

a cold plate attached to the first semiconductor device and the device stack;

wherein the cold plate comprises:

an inlet opening;

an outlet opening; and

a patterned first side and an opposite second side;

wherein:

the patterned first side comprises a base surface and sidewalls extending downwardly from the base surface;

the base surface is spaced apart from the first semiconductor device and the device stack to collectively define a coolant channel therebetween; and

the coolant channel is in fluid communication with the inlet opening and the outlet opening; and

wherein the device stack is attached to the first side of the cold plate in a side-by-side arrangement with the first semiconductor device, and the cold plate extends laterally beyond the first semiconductor device and the device stack.

25 . The integrated cooling assembly of claim 24 , wherein the cold plate is attached to the first semiconductor device by direct dielectric bonds.

26 . The integrated cooling assembly of claim 24 , wherein the cold plate is attached to the first semiconductor device by direct hybrid bonds.

27 . The integrated cooling assembly of claim 24 , further comprising a coolant fluid disposed in the coolant channel.

28 . The integrated cooling assembly of claim 24 , wherein the inlet and outlet openings comprise portions of a fluid flow path that further comprises the coolant channel.

29 . The integrated cooling assembly of claim 28 , wherein the inlet and outlet openings extend between the first side and the second side of the cold plate.

30 . The integrated cooling assembly of claim 28 , wherein the inlet and outlet openings comprise gaps between the first side of the cold plate and the first semiconductor device and the device stack.

31 . The integrated cooling assembly of claim 28 , wherein the first side of the cold plate further comprises a plurality of protruding features that extend downwardly from the base surface to disrupt at least portions of the fluid flow path through the coolant channel.

32 . The integrated cooling assembly of claim 31 , wherein the protruding features are directly bonded to the first semiconductor device.

33 . The integrated cooling assembly of claim 30 , wherein the gaps are disposed at opposite ends of the base surface.

34 . The integrated cooling assembly of claim 24 , further comprising:

a package substrate; and

a package cover disposed on the package substrate, the package cover having an inlet opening and an outlet opening disposed therethrough an outlet opening disposed therethrough,

wherein the package cover comprises one or more coolant line attachment features.

35 . The integrated cooling assembly of claim 24 , further comprising an underfill layer that at least partially encapsulates the integrated cooling assembly in regions outside of the coolant channel.

36 . The integrated cooling assembly of claim 34 , further comprising:

a material layer disposed between the package cover and the cold plate,

wherein the material layer forms an impermeable barrier between the package cover and the cold plate.

37 . The integrated cooling assembly of claim 24 , wherein a side surface of the cold plate and the first semiconductor device are substantially flush with one another.

38 . The integrated cooling assembly of claim 24 , wherein the cold plate is attached to the device stack by direct dielectric bonds.

39 . The integrated cooling assembly of claim 24 , wherein the cold plate is attached to the device stack by direct hybrid bonds.

40 . A device package comprising:

a package substrate;

a package cover disposed on the package substrate, the package cover having an inlet opening and an outlet opening disposed therethrough;

an integrated cooling assembly disposed between the package substrate and the package cover, the integrated cooling assembly comprising a first semiconductor device, a plurality of second semiconductor devices vertically arranged in a device stack and a cold plate attached to the first semiconductor device and the device stack; and

a material layer disposed between the package cover and the cold plate, wherein:

the cold plate comprises a patterned first side and an opposite second side;

the patterned first side comprises a base surface and sidewalls extending downwardly from the base surface;

the base surface is spaced apart from the first semiconductor device and the device stack to collectively define a coolant channel therebetween;

the coolant channel is in fluid communication with the inlet opening and the outlet opening through openings disposed through respective portions of the material layer; and

wherein the device stack is attached to the first side of the cold plate in a side-by-side arrangement with the first semiconductor device, and the cold plate extends laterally beyond the first semiconductor device and the device stack.

41 . The device package of claim 40 , wherein the cold plate is attached to the first semiconductor device by direct dielectric bonds.

42 . The device package of claim 40 , wherein the cold plate is attached to the first semiconductor device by direct hybrid bonds.

43 . The device package of claim 40 , wherein the cold plate is attached to the device stack by direct dielectric bonds.

Assignments (2)
SECURITY INTEREST Recorded May 28, 2025
From: ADEIA INC. (F/K/A XPERI HOLDING CORPORATION); ADEIA HOLDINGS INC.; ADEIA MEDIA HOLDINGS INC.; ADEIA IMAGING LLC; ADEIA MEDIA LLC; ADEIA MEDIA SOLUTIONS INC.; ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.; ADEIA TECHNOLOGIES INC.; ADEIA GUIDES INC.; ADEIA SOLUTIONS LLC; ADEIA SEMICONDUCTOR ADVANCED TECHNOLOGIES INC.; ADEIA SEMICONDUCTOR SOLUTIONS LLC; ADEIA SEMICONDUCTOR INTELLECTUAL PROPERTY LLC; ADEIA SEMICONDUCTOR TECHNOLOGIES LLC; ADEIA PUBLISHING INC.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 071454/0343 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: HABA, BELGACEM
To: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Reel/Frame 069422/0062 →