NON-VOLATILE MEMORY WITH DYNAMIC ERASE VOLTAGE
A non-volatile memory system adjusts a subset of memory cells, while reducing disturbs to memory cells inhibited from the adjustment, by applying adjustment voltages for different lengths of time based on current condition of the memory cells.
1 . A non-volatile storage apparatus, comprising:
a selected word line;
bit lines;
a plurality of non-volatile memory cells connected to the selected word line and the bit lines; and
a control circuit connected to the selected word line, the bit lines and the non-volatile memory cells;
the control circuit is configured to concurrently:
apply a selected erase voltage to the selected word line,
apply a first erase voltage for a first time duration to a first set of the bit lines, and
apply a second erase voltage for a second time duration to a second set of the bit lines, the first time duration is different than the second time duration, the first set of the bit lines is different than the second set of the bit lines.
2 . The non-volatile storage apparatus of claim 1 , wherein:
the first time duration is shorter than the second time duration.
3 . The non-volatile storage apparatus of claim 1 , wherein:
the first erase voltage is equal in magnitude to the second erase voltage.
4 . The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration by:
applying the first erase voltage to the first set of the bit lines from a first time to a second time,
applying an inhibit voltage to the first set of the bit lines from the second time to a third time,
applying the second erase voltage to the second set of the bit lines from the first time to the third time.
5 . The non-volatile storage apparatus of claim 1 , wherein:
the first erase voltage and the second erase voltage are derived from a same charge pump.
6 . The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to apply a first erase voltage for a first time duration to a first set of the bit lines by applying one or more erase voltage pulses of a first time duration at a first voltage magnitude to the first set of the bit lines; and
the control circuit is configured to apply a second erase voltage for a second time duration to a second set of the bit lines by applying one or more erase voltage pulses of a second time duration at a second voltage magnitude to the second set of the bit lines.
7 . The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration in order to adjust non-volatile memory cells connected to the first set of the bit lines and the second set of the bit lines; and
the control circuit is further configured apply an inhibit voltage for the second time duration to a third set of the bit lines concurrently while applying the first erase voltage for the first time duration and applying the second erase voltage for the second time duration in order to inhibit adjustment of the non-volatile memory cells connected to the third set of the bit lines.
8 . The non-volatile storage apparatus of claim 7 , wherein:
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration by:
applying the first erase voltage to the first set of the bit lines from a first time to a second time,
applying the inhibit voltage to the first set of the bit lines from the second time to a third time,
applying the second erase voltage to the second set of the bit lines from the first time to the third time, and
applying the inhibit voltage to the third set of the bit lines from the first time to the third time.
9 . The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration by applying one or more erase voltage pulses at an erase enable voltage magnitude to a first subset of the plurality of non-volatile memory cells connected to the first set of the bit lines and to a second subset of the plurality of non-volatile memory cells connected to the second set of the bit lines such that pulse widths of the erase voltage pulses at the erase enable voltage magnitude are truncated for first subset of the plurality of non-volatile memory cells and pulse widths of the erase voltage pulses at the erase enable voltage magnitude are not truncated for second subset of the plurality of non-volatile memory cells.
10 . The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is further configured to sense the plurality of non-volatile memory cells to determine whether the non-volatile memory cells are at lower threshold voltages or higher threshold voltages, the first set of the bit lines are connected to the non-volatile memory cells determined to be at the lower threshold voltages, the second set of the bit lines are connected to the non-volatile memory cells determined to be at the higher threshold voltages.
11 . The non-volatile storage apparatus of claim 10 , wherein:
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration in order to adjust non-volatile memory cells connected to the first set of the bit lines and the second set of the bit lines; and
the control circuit is further configured apply an inhibit voltage to a third set of the bit lines concurrently while applying the first erase voltage for the first time duration and applying the second erase voltage for the second time duration in order to inhibit adjustment of non-volatile memory cells connected to the third set of the bit lines.
12 . The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration in order to lower threshold voltages of non-volatile memory cells connected to the first set of the bit lines and non-volatile memory cells connected the second set of the bit lines.
13 . The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration in order to partially erase non-volatile memory cells connected to the first set of the bit lines and non-volatile memory cells connected the second set of the bit lines.
14 . The non-volatile storage apparatus of claim 1 , wherein:
the plurality of non-volatile memory cells are configured to be programmed to a common threshold voltage distribution; and
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration in order to tighten the common threshold voltage distribution.
15 . The non-volatile storage apparatus of claim 1 , wherein:
the plurality of non-volatile memory cells are configured to be programmed to one or more data states; and
the control circuit is configured to apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration in order to change data states of the non-volatile memory cells connected to the first set of the bit lines and non-volatile memory cells connected the second set of the bit lines.
16 . The non-volatile storage apparatus of claim 1 , wherein:
the control circuit include sensing circuits and bit line interface circuits;
the bit line interface circuits each connect one sensing circuit and one or more voltage sources to one bit line;
the control circuit is configured apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration by:
applying an erase enable voltage to the bit line interface circuits,
configuring the bit line interface circuits to pass the erase enable voltage to respective bit lines at a first time,
configuring the bit line interface circuits to float all of the bit lines at a second time after the first time,
configuring bit line interface circuits connected to the first set of the bit lines to provide a path to discharge the respective connected bit lines at the second time, and configuring bit line interface circuits connected to the second set of the bit lines to maintain respective connected bit lines at the erase enable voltage until a third time that is after the second time.
17 . The non-volatile storage apparatus of claim 1 , wherein:
the control circuit comprises a charge pump connected to a first transfer and a second transfer gate;
the control circuit is configured apply the first erase voltage for the first time duration and apply the second erase voltage for the second time duration by:
applying a first gate voltage to the first transfer gate at a first time until a second time,
applying a second gate voltage to the first transfer gate at the second time until a third time, and
applying the first gate voltage to the second transfer gate at the first time until the third time.
18 . A method, comprising:
sensing a set of non-volatile memory cells connected to a selected word line to determine whether the non-volatile memory cells are at lower threshold voltages or higher threshold voltages;
applying a selected erase voltage to the selected word line;
after the sensing, applying one or more erase voltage pulses of a first time duration at a first voltage magnitude to non-volatile memory cells determined to be at the lower threshold voltages in order to lower threshold voltages of the non-volatile memory cells determined to be at the lower threshold voltages;
after the sensing, applying one or more erase voltage pulses of a second time duration at the first voltage magnitude to non-volatile memory cells determined to be at the higher threshold voltages in order to lower threshold voltages of the non-volatile memory cells determined to be at the higher threshold voltages, the first time duration is different than the second time duration; and
applying one or more voltages pulses at an inhibit voltage to other non-volatile memory cells connected to the selected word line that are to be inhibited from changing threshold voltage.
19 . The method of claim 18 , wherein:
the applying one or more erase voltage pulses of a first time duration at a first voltage magnitude to non-volatile memory cells determined to be at the lower threshold voltages comprises applying an erase enable voltage to non-volatile memory cells determined to be at the lower threshold voltages from a first time to a second time and applying the inhibit voltage to non-volatile memory cells determined to be at the lower threshold voltages from the second time to a third time;
the applying one or more erase voltage pulses of a second time duration at the first voltage magnitude to non-volatile memory cells determined to be at the higher threshold voltages comprises applying the erase enable voltage to the non-volatile memory cells determined to be at the higher threshold voltages from the first time to the third time; and
the applying one or more voltages pulses at a third voltage magnitude to other non-volatile memory cells comprises applying the inhibit voltage to the other non-volatile memory cells from the first time to the third time.
20 . A non-volatile storage apparatus, comprising:
a selected word line;
bit lines;
a plurality of non-volatile memory cells connected to the selected word line and the bit lines, the plurality of non-volatile memory cells are configured to be programmed to a common threshold voltage distribution; and
means for tightening the common threshold voltage distribution by applying one or more erase voltage pulses to a first subset of the plurality of non-volatile memory cells such that pulse widths of the erase voltage pulses at an erase enable voltage magnitude are truncated for non-volatile memory cells of the first subset with lower threshold voltages and pulse widths of the erase voltage pulses at the erase enable voltage magnitude are not truncated for non-volatile memory cells of the first subset with higher threshold voltages, while not adjusting threshold voltages of a second subset of the plurality of non-volatile memory cells.