Ramp generator and image sensing device
A ramp generator includes a digital-to-analog converter, a first capacitor, a second capacitor and a noise cancellation circuit. The digital-to-analog converter is configured to generate a ramp-up voltage signal on a first output terminal and a ramp-down voltage signal on a second output terminal. The first capacitor is coupled between the first output terminal and an intermediate node. The second capacitor is coupled between the second output terminal and the intermediate node. The noise cancellation circuit is coupled with the intermediate node. The noise cancellation circuit is configured to provide a compensation feedback according to an intermediate voltage on the intermediate node.
1 . A ramp generator, comprising:
a digital-to-analog converter, having a first output terminal and a second output terminal, and configured to generate a ramp-up voltage signal on the first output terminal and a ramp-down voltage signal on the second output terminal;
a first capacitor, coupled between the first output terminal and an intermediate node;
a second capacitor, coupled between the second output terminal and the intermediate node; and
a noise cancellation circuit, coupled with the intermediate node, and configured to provide a compensation feedback according to an intermediate voltage on the intermediate node, wherein the compensation feedback is correlated to an alternating-current component of the intermediate voltage, the compensation feedback is configured for compensating an intrinsic noise of the digital-to-analog converter.
2 . The ramp generator of claim 1 , wherein the digital-to-analog converter comprises a plurality of digital-to-analog converter units, each of the digital-to-analog converter units comprises a first current source, a first transistor and a second transistor, the first transistor in each of the digital-to-analog converter units is controlled by one code bit of a first digital code for generating the ramp-up voltage signal, the second transistor in each of the digital-to-analog converter units is controlled by one code bit of a second digital code for generating the ramp-down voltage signal.
3 . The ramp generator of claim 2 , wherein the noise cancellation circuit comprises:
a third transistor, wherein a drain terminal and a gate terminal of the third transistor are connected to a second current source for forming a bias voltage;
a switch, coupled between the third transistor and the intermediate node; and
a plurality of fourth transistors, wherein gate terminals of the fourth transistors are connected together to the intermediate node, each of drain terminals of the fourth transistors is connected to the first current source in each of the digital-to-analog converter units.
4 . The ramp generator of claim 3 , wherein the switch is configured to reset a direct-current level of the intermediate voltage on the intermediate node according to the bias voltage, and
each of the fourth transistors is configured to form a diverged current to suppress an operating current of the digital-to-analog converter.
5 . The ramp generator of claim 2 , wherein the noise cancellation circuit comprises:
a low-dropout regulator;
a fifth transistor, wherein a drain terminal and a gate terminal of the fifth transistor are connected to a third current source for forming a bias voltage, a source terminal of the fifth transistor is connected to the low-dropout regulator;
a switch, coupled between the fifth transistor and the intermediate node; and
a plurality of sixth transistors, wherein gate terminals of the sixth transistors are connected together to the intermediate node, each of drain terminals of the sixth transistors is connected to the first current source in each of the digital-to-analog converter units.
6 . The ramp generator of claim 5 , wherein the switch is configured to reset a direct-current level of the intermediate voltage on the intermediate node according to the bias voltage, and
each of the sixth transistors is configured to form a supplemental current to the digital-to-analog converter, wherein a current amplitude of the supplemental current is negatively correlated with the alternating-current component of the intermediate voltage.
7 . The ramp generator of claim 1 , wherein the ramp generator is configured to generate a ramp output signal to an image readout circuit, the image readout circuit comprises:
a buffer stage, coupled to the ramp generator, and configured to generate a ramp buffer signal according to the ramp output signal;
a readout comparator, coupled to the buffer stage and a photoelectric sensing pixel, and configured to compare a pixel sensing voltage from the photoelectric sensing pixel with the ramp buffer signal for generating a comparison result; and
a counter, coupled to the readout comparator, and configured to generate a digital output signal according to the comparison result, the digital output signal is configured to indicate a gray level or a brightness level of the pixel sensing voltage.
8 . The ramp generator of claim 7 , wherein the noise cancellation circuit comprises:
a low-dropout regulator;
a seventh transistor, wherein a drain terminal and a gate terminal of the seventh transistor are connected to a fourth current source for forming a bias voltage, a source terminal of the seventh transistor is connected to the low-dropout regulator;
a switch, coupled between the seventh transistor and the intermediate node; and
an eighth transistor, wherein a gate terminal of the eighth transistor is connected to the intermediate node, a drain terminal of the eighth transistor is connected to the buffer stage.
9 . The ramp generator of claim 8 , wherein the buffer stage comprises a ninth transistor, wherein a gate terminal of the ninth transistor is configured to receive the ramp output signal, a drain terminal of the ninth transistor is configured to generate the ramp buffer signal,
wherein the switch is configured to reset a direct-current level of the intermediate voltage on the intermediate node according to the bias voltage,
the eighth transistor is configured to form a supplemental voltage to the drain terminal of the ninth transistor, wherein a voltage level of the supplemental voltage is negatively correlated with the alternating-current component of the intermediate voltage.
10 . The ramp generator of claim 7 , wherein the readout comparator comprises a first comparator, a second comparator and an inverter,
wherein the noise cancellation circuit comprises:
a third capacitor, coupled between a negative input of the first comparator and the intermediate node;
a fourth capacitor, coupled between a positive input of the first comparator and a signal source of a bias voltage; and
a switch, coupled between the signal source of the bias voltage and the intermediate node.
11 . The ramp generator of claim 10 , wherein the switch is configured to reset a direct-current level of the intermediate voltage on the intermediate node according to the bias voltage,
the third capacitor is configured to form a supplemental voltage to the negative input of the first comparator, wherein a voltage level of the supplemental voltage is positively correlated with the alternating-current component of the intermediate voltage.
12 . An image sensing device, comprising:
a ramp generator, configured to generate a ramp output signal, wherein the ramp generator comprises:
a digital-to-analog converter, having a first output terminal and a second output terminal, and configured to generate a ramp-up voltage signal on the first output terminal and a ramp-down voltage signal on the second output terminal, wherein the ramp output signal is generated according to the ramp-up voltage signal or the ramp-down voltage signal;
a first capacitor, coupled between the first output terminal and an intermediate node;
a second capacitor, coupled between the second output terminal and the intermediate node; and
a noise cancellation circuit, coupled with the intermediate node, and configured to provide a compensation feedback according to an intermediate voltage on the intermediate node, wherein the compensation feedback is correlated to an alternating-current component of the intermediate voltage, the compensation feedback is configured for compensating an intrinsic noise of the digital-to-analog converter; and
an image readout circuit, coupled to the ramp generator and a photoelectric sensing pixel, the image readout circuit is configured to sample a pixel sensing voltage from the photoelectric sensing pixel in reference with the ramp output signal from the ramp generator, so as to generate a digital output signal.
13 . The image sensing device of claim 12 , wherein the image readout circuit comprises:
a buffer stage, coupled to the ramp generator, and configured to generate a ramp buffer signal according to the ramp output signal;
a readout comparator, coupled to the buffer stage and the photoelectric sensing pixel, and configured to compare the pixel sensing voltage from the photoelectric sensing pixel with the ramp buffer signal for generating a comparison result; and
a counter, coupled to the readout comparator, and configured to generate the digital output signal according to the comparison result, the digital output signal is configured to indicate a gray level or a brightness level of the pixel sensing voltage.
14 . The image sensing device of claim 13 , wherein the digital-to-analog converter comprises a plurality of digital-to-analog converter units, each of the digital-to-analog converter units comprises a first current source, a first transistor and a second transistor, the first transistor in each of the digital-to-analog converter units is controlled by one code bit of a first digital code for generating the ramp-up voltage signal, the second transistor in each of the digital-to-analog converter units is controlled by one code bit of a second digital code for generating the ramp-down voltage signal.
15 . The image sensing device of claim 14 , wherein the noise cancellation circuit comprises:
a third transistor, wherein a drain terminal and a gate terminal of the third transistor are connected to a second current source for forming a bias voltage;
a switch, coupled between the third transistor and the intermediate node; and
a plurality of fourth transistors, wherein gate terminals of the fourth transistors are connected together to the intermediate node, each of drain terminals of the fourth transistors is connected to the first current source in each of the digital-to-analog converter units.
16 . The image sensing device of claim 14 , wherein the noise cancellation circuit comprises:
a low-dropout regulator;
a fifth transistor, wherein a drain terminal and a gate terminal of the fifth transistor are connected to a third current source for forming a bias voltage, a source terminal of the fifth transistor is connected to the low-dropout regulator;
a switch, coupled between the fifth transistor and the intermediate node; and
a plurality of sixth transistors, wherein gate terminals of the sixth transistors are connected together to the intermediate node, each of drain terminals of the sixth transistors is connected to the first current source in each of the digital-to-analog converter units.
17 . The image sensing device of claim 13 , wherein the noise cancellation circuit comprises:
a low-dropout regulator;
a seventh transistor, wherein a drain terminal and a gate terminal of the seventh transistor are connected to a fourth current source for forming a bias voltage, a source terminal of the seventh transistor is connected to the low-dropout regulator;
a switch, coupled between the seventh transistor and the intermediate node; and
an eighth transistor, wherein a gate terminal of the eighth transistor is connected to the intermediate node, a drain terminal of the eighth transistor is connected to the buffer stage.
18 . The image sensing device of claim 13 , wherein the readout comparator comprises a first comparator, a second comparator and an inverter,
wherein the noise cancellation circuit comprises:
a third capacitor, coupled between a negative input of the first comparator and the intermediate node;
a fourth capacitor, coupled between a positive input of the first comparator and a signal source of a bias voltage; and
a switch, coupled between the signal source of the bias voltage and the intermediate node.