Gate driving circuit, display device including the same, and electronic device including the display device
A gate driver includes a pull-up control circuit configured to apply a previous carry signal to a pull-up control node in response to the previous carry signal among carry signals of previous gate drivers, a buffer transistor configured to output a gate clock signal as a gate output signal in response to a signal of the pull-up control node, and including an upper gate electrode connected to the pull-up control node and a lower gate electrode connected to a stabilization node, a first stabilization transistor including a gate electrode connected to the pull-up control node and a first electrode connected to the stabilization node, and a second stabilization transistor including a gate electrode connected to a pull-down control node and a first electrode connected to the stabilization node.
1 . A gate driver comprising:
a pull-up control circuit configured to apply a previous carry signal to a pull-up control node in response to the previous carry signal of a previous gate driver;
a buffer transistor configured to output a gate clock signal as a gate output signal in response to a signal of the pull-up control node, and comprising an upper gate electrode connected to the pull-up control node, and a lower gate electrode connected to a stabilization node;
a first stabilization transistor comprising a gate electrode connected to the pull-up control node, and a first electrode connected to the stabilization node; and
a second stabilization transistor comprising a gate electrode connected to a pull-down control node, and a first electrode connected to the stabilization node.
2 . The gate driver of claim 1 , wherein the pull-up control circuit comprises:
a first pull-up control transistor comprising a gate electrode to which the previous carry signal is configured to be applied, a first electrode to which the previous carry signal is configured to be applied, and a second electrode; and
a second pull-up control transistor comprising a gate electrode to which the previous carry signal is configured to be applied, a first electrode connected to the pull-up control node, and a second electrode connected to the second electrode of the first pull-up control transistor.
3 . The gate driver of claim 2 , further comprising:
a substrate;
a first lower metal layer above the substrate; and
a second lower metal layer above the first lower metal layer, and comprising the lower gate electrode of the buffer transistor,
wherein an active pattern of the second pull-up control transistor and the gate electrode of the second pull-up control transistor are between the first lower metal layer and the second lower metal layer in a cross-sectional view, and
wherein an active pattern of the buffer transistor and the upper gate electrode of the buffer transistor are above the second lower metal layer.
4 . The gate driver of claim 3 , further comprising a connection electrode electrically connecting the upper gate electrode of the buffer transistor and the second electrode of the second pull-up control transistor.
5 . The gate driver of claim 4 , wherein the connection electrode contacts the gate electrode of the first stabilization transistor.
6 . The gate driver of claim 4 , wherein the connection electrode is separated from the second lower metal layer in a cross-sectional view.
7 . The gate driver of claim 4 , wherein a first electrode of the buffer transistor and a second electrode of the buffer transistor are above the connection electrode.
8 . The gate driver of claim 4 , wherein the first stabilization transistor further comprises a second electrode to which a high gate voltage defining a high level of the gate output signal is configured to be applied.
9 . The gate driver of claim 8 , wherein the second electrode of the first stabilization transistor is above the connection electrode.
10 . The gate driver of claim 4 , wherein the first stabilization transistor further comprises a second electrode connected to the pull-up control node.
11 . The gate driver of claim 10 , wherein the connection electrode comprises the second electrode of the first stabilization transistor.
12 . The gate driver of claim 11 , wherein the second electrode of the first stabilization transistor is at a same layer as the connection electrode.
13 . The gate driver of claim 3 , wherein the second lower metal layer overlaps the second electrode of the second pull-up control transistor.
14 . The gate driver of claim 1 , wherein the second stabilization transistor further comprises a second electrode configured to receive a low voltage.
15 . A display device comprising:
a substrate comprising a display area, and a peripheral area adjacent to the display area;
a first lower metal layer in the peripheral area above the substrate;
a pull-up control transistor in the peripheral area above the first lower metal layer, and comprising a first active pattern, and a first gate electrode above the first active pattern;
a second lower metal layer in the peripheral area above the first gate electrode of the pull-up control transistor;
a buffer transistor in the peripheral area above the second lower metal layer, and comprising a second active pattern overlapping the second lower metal layer, and a second gate electrode above the second active pattern;
a first stabilization transistor in the peripheral area above the second lower metal layer, and comprising a third active pattern overlapping the second lower metal layer, and a third gate electrode above the third active pattern;
a connection electrode above the second gate electrode and the third gate electrode, and contacting the second gate electrode and the third gate electrode; and
a light-emitting element in the display area above the connection electrode.
16 . The display device of claim 15 , wherein the connection electrode is separated from the second lower metal layer.
17 . The display device of claim 15 , wherein the connection electrode contacts a portion of the third active pattern.
18 . The display device of claim 15 , further comprising a second stabilization transistor in the peripheral area above the second lower metal layer, and comprising a fourth active pattern overlapping the second lower metal layer, and a fourth gate electrode above the fourth active pattern,
wherein the third active pattern, the fourth active pattern, and the second lower metal layer are electrically connected.
19 . The display device of claim 18 , further comprising:
at least one pixel comprising the light-emitting element in the display area;
a gate driver configured to output a gate output signal, in the peripheral area, and comprising the pull-up control transistor, the buffer transistor, the first stabilization transistor, and the second stabilization transistor; and
a gate line configured to transmit the gate output signal to the pixel.
20 . An electronic device comprising:
a display panel comprising at least one pixel, a gate line electrically connected to the pixel, or a data line electrically connected to the pixel;
a gate driver configured to output a gate output signal to the gate line, and comprising:
a pull-up control circuit configured to apply a previous carry signal to a pull-up control node in response to the previous carry signal of a previous gate driver;
a buffer transistor configured to output a gate clock signal as the gate output signal in response to a signal of the pull-up control node, and comprising an upper gate electrode connected to the pull-up control node, and a lower gate electrode connected to a stabilization node;
a first stabilization transistor comprising a gate electrode connected to the pull-up control node, and a first electrode connected to the stabilization node; and
a second stabilization transistor comprising a gate electrode connected to a pull-down control node, and a first electrode connected to the stabilization node;
a data driver configured to output a data voltage to the data line;
a driving controller configured to control the display panel, the gate driver, and the data driver; and
a processor configured to output input image data and an input control signal to the driving controller.