IP Library Granted Patent US 11,087,696
Granted Patent B2
US 11,087,696 · App. 16/739,012 · Granted Aug 10, 2021

Display device and method of manufacturing the same

Inventors: Myoung Hwa Kim (Seoul, KR); Masataka Kano (Hwaseong-si, KR); Yeon Keon Moon (Hwaseong-si, KR); Joon Seok Park (Yongin-si, KR); Jun Hyung Lim (Seoul, KR); Hye Lim Choi (Yongin-si, KR)
Assignee: Samsung Display Co., Ltd.
G09G3/3291G09G3/3266H01L51/5281H01L51/56H01L2251/308
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Quick Facts
Patent No.
US 11,087,696
App. No.
16/739,012
Granted
Aug 10, 2021
Kind
B2
Abstract

A display device including: a pixel connected to a scan line and a data line intersecting the scan line. The pixel includes a light emitting element and a driving transistor which controls a driving current supplied to the light emitting element according to a data voltage applied from the data line. The driving transistor includes a first active layer including an oxide semiconductor doped with a metal.

Claims (46)

1. A display device comprising a pixel connected to a scan line and a data line intersecting the scan line,

wherein:

the pixel comprises:

a light emitting element and a driving transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line; and

a scan transistor for applying the data voltage of the data line to a first gate electrode of the driving transistor according to a scan signal transmitted to the scan line;

the driving transistor comprises a first active layer including an oxide semiconductor doped with a metal;

the scan transistor comprises:

a second active layer having an oxide semiconductor;

a second light shielding layer disposed under the second active layer; and

a second gate electrode disposed on the second active layer; and

the second gate electrode contacts the second light shielding layer through a sixth contact hole passing through a gate insulating layer disposed between the second active layer and the second gate electrode and an insulating layer disposed between the second active layer and the second light shielding layer.

2. The display device of claim 1 , wherein the proportion of the metal in the first active layer is about 10 atomic % or less.

3. The display device of claim 1 , wherein the metal is copper (Cu), arsenic (As), antimony (Sb), lanthanum (La), a mixture of silver (Ag) and nitrogen (N), a mixture of boron (B) and nitrogen (N), or a mixture of gallium (Ga) and nitrogen (N).

4. The display device of claim 1 , wherein the metal is copper (Cu), and the oxide semiconductor comprises tin (Sn).

5. The display device of claim 4 , wherein the first active layer comprises indium-gallium-tin oxide (IGTO) or indium-gallium-zinc-tin oxide (IGZTO).

6. The display device of claim 1 , wherein the metal is doped into an upper surface of the first active layer.

7. The display device of claim 6 , wherein the metal is doped into at least one side surface of the first active layer.

8. The display device of claim 1 , wherein the first active layer comprises a first conducting region, a second conducting region, and a channel region disposed between the first conducting region and the second conducting region.

9. The display device of claim 8 , wherein the driving transistor comprises:

a first light shielding layer disposed under the first active layer;

a first gate electrode disposed on the first active layer;

a first source electrode connected to the first conducting region through a first contact hole passing through an interlayer insulating film disposed on the first gate electrode; and

a first drain electrode connected to the second conducting region through a second contact hole passing through the interlayer insulating film.

10. The display device of claim 9 , wherein the first source electrode contacts the first light shielding layer through a third contact hole passing through the interlayer insulating film and an insulating layer disposed between the first active layer and the first light shielding layer.

11. The display device of claim 1 , wherein the second active layer is not doped with the metal.

12. The display device of claim 1 , further comprising a scan driver circuit configured to output a scan signal to the scan line,

wherein:

the scan driver circuit comprises a pull-up transistor configured to output a gate-on voltage when the pull-up transistor is charged with the gate-on voltage; and

the pull-up transistor comprises a third active layer including an oxide semiconductor.

13. The display device of claim 12 , wherein the third active layer is not doped with the metal.

14. The display device of claim 12 , wherein the pull-up transistor further comprises:

a third light shielding layer disposed under the third active layer; and

a third gate electrode disposed on the third active layer.

15. A display device comprising:

a pixel connected to a scan line and a data line intersecting the scan line; and

a scan driver circuit configured to output a scan signal to the scan line,

wherein:

the pixel comprises a light emitting element and a driving transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line;

the driving transistor comprises a first active layer including an oxide semiconductor doped with a metal;

the scan driver circuit comprises a pull-up transistor configured to output a gate-on voltage when the pull-up transistor is charged with the gate-on voltage;

the pull-up transistor comprises:

a third active layer including an oxide semiconductor;

a third light shielding layer disposed under the third active layer; and

a third gate electrode disposed on the third active layer; and

the third gate electrode contacts the third light shielding layer through a ninth contact hole passing through a gate insulating layer disposed between the third active layer and the third gate electrode and an insulating layer disposed between the third active layer and the third light shielding layer.

16. The display device of claim 1 , further comprising a data voltage distribution circuit which comprises a first distribution transistor connected between a routing line and the data line and a second distribution transistor connected between the routing line and another data line adjacent to the data line, wherein each of the first distribution transistor and the second distribution transistor comprises a fourth active layer including polysilicon.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2020
From: KIM, MYOUNG HWA; KANO, MASATAKA; MOON, YEON KEON; PARK, JOON SEOK; LIM, JUN HYUNG; CHOI, HYE LIM
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 051554/0763 →
Priority Claims (1)
KR 10-2019-0006406 · Jan 17, 2019 · national
Continuity (1)
Related Publication 20200234654A1 · Jul 23, 2020
Cited By (1)
US 12,633,253