Type I-II transistor with a manufacturable ledge
A transistor comprising a plurality of semiconductor layers arranged to form a base, an emitter and a collector wherein the emitter is of a first semiconductor material and comprises an emitter ledge being made from a material which is selectively etchable relative to the emitter or base material to produce the emitter ledge that is lattice matched.
1 . A heterojunction bipolar transistor comprising a plurality of semiconductor layers, selected from an InP-based materials system, arranged to form a base, an emitter and a collector wherein the emitter has a graded emitter structure comprising an emitter ledge, the emitter ledge comprising a layer of an etch selective material which is selectively etchable relative to at least one of the materials of the emitter and the base:
wherein the collector and the emitter comprise InP, the base comprises GaAsSb, the emitter ledge comprises InAIP, and wherein the etch selective material is of the emitter ledge and is selected from a set of Al containing quaternary semiconductor materials (Al-Q) of said InP-based materials system, having a conduction band-similar to a point in the emitter layer at a ledge etch point for a specific composition of InAlP.
2 . The transistor of claim 1 , wherein materials of the emitter ledge and the emitter are substantially lattice matched.
3 . The transistor of claim 1 , wherein a position of the etch selective material within the emitter material is where a conduction band of the emitter is matched with a conduction band of the Al-Q material.
4 . The transistor of claim 1 , wherein the emitter ledge comprises a bulk material or a superlattice material.
5 . The transistor of claim 4 , wherein the superlattice material comprises a chirped superlattice.
6 . The transistor of claim 1 , wherein the etch selective material is located intermediate the graded emitter structure to form the emitter ledge.
7 . The transistor of claim 1 , wherein the emitter ledge has a predetermined bandgap energy profile including one or more of: at least two sloped regions separated by an intermediate region (“notch”) of the emitter ledge.
8 . The transistor of claim 1 , wherein the emitter ledge comprises a graded emitter comprising a lightly doped AlInP layer and the etch selective material extends through the lightly doped AlInP layer.
9 . The transistor of claim 1 , wherein the base material comprises GaAs(x)Sb(1-x).
10 . The transistor of claim 1 , wherein the graded emitter comprises In(1-x)Al(x)P, the etch selective material is InGaAlAs and the etch selective material is sandwiched between the In(1-x)Al(x)P.
11 . The transistor of claim 1 , wherein the layers on at least one side of the emitter ledge comprise GaAs(x)Sb(1-x) or other arsenide-based material.
12 . The transistor of claim 11 , wherein the layers of arsenide-based material are on either side of the emitter ledge.
13 . The transistor of claim 1 , wherein the transistor is a transistor of one of a Transimpedance Amplifier (TIA) in an optical receiver and an Electro-Absorption Modulator (EAM) driver in an optical transmitter.
14 . An electro-photonic device comprising one of a monolithically integrated photodiode (PD); a monolithically integrated Electro-Absorption Modulator (EAM) or a monolithically integrated Mach-Zehnder modulator (MZM) and electronics comprising a transistor according to claim 1 .
15 . The electro-photonic device of claim 14 , wherein the device is a receiver and wherein the transistor comprises a Transimpedance Amplifier (TIA).
16 . The electro-photonic device of claim 15 , wherein an epitaxial layer stack is formed on a semi-insulating (SI) InP substrate;
the TIA comprises heterojunction bipolar transistors (HBT) formed by a first plurality of semiconductor layers of the epitaxial layer stack formed on the SI substrate;
the PD comprises a p-i-n diode (PIN) formed by a second plurality of semiconductor layers of the epitaxial layer stack overlying the first plurality of semiconductor layers, the second plurality of semiconductor layers comprising an n-layer, an i-layer and a p-layer; and
a p-contact of the PIN diode is directly interconnected by a conductive trace to an input of the TIA.
17 . The electro-photonic device of claim 16 further comprising a spacer comprising one or more intermediate layers comprising a semi-insulating layer between the first plurality of semiconductor layers and the second plurality of semiconductor layers.
18 . The electro-photonic device of claim 17 , wherein the TIA is formed on a first area of the substrate, and the PIN is provided on an adjacent area and comprising an isolation region electrically isolating the first plurality of semiconductor layers of the first area from the first plurality of semiconductor layers of the adjacent area.
19 . The electro-photonic device of claim 14 , wherein the device is a transmitter and wherein the transistor comprises a transistor of an Electro-Absorption Modulator (EAM) driver.
20 . The electro-photonic device of claim 19 , further comprising a plurality of semiconductor layers formed on a semi-insulating (SI) substrate, the plurality of semiconductor layers comprising a first plurality of semiconductor layers defining an optical waveguide forming at least part of the EAM; and a second plurality of semiconductor layers comprising EAM driver layers.
21 . The electro-photonic device of claim 20 , further comprising a spacer separating the first plurality of semiconductor layers from the second plurality of semiconductor layers.
22 . The electro-photonic device of claim 19 , further comprising a laser or a laser source.
23 . An optical system comprising at least one electro-photonic device as defined in claim 14 .
24 . The optical system of claim 23 , comprising two or more electro-photonic devices.
25 . A method a manufacturing a transistor according to claim 1 , the method comprising: growing a collector and a base;
forming a graded emitter over the base;
providing an etch selective material intermediately through the graded emitter;
performing a selective etch of the graded emitter and the etch selective material to form an emitter ledge at an intermediate position in the graded emitter.
26 . The method of claim 25 , further comprising one or more of:
growing the collector and base by one or more epitaxial growth process stages; forming a graded emitter over the base from a combination of layers;
forming the graded emitter to comprise a lightly doped AlInP layer and a heavily doped InP layer;
etching selective the graded emitter or the base by an etchant that works selectively on the materials of the graded emitter or the base;
selecting the etch selective material, so that a selective wet etch can be used to selectively etch layers to define the emitter ledge consistently for a predetermined combination of emitter ledge and emitter material;
wherein the epitaxial process comprises one of a molecular-beam epitaxy (MBE) process or a Metal Organic Chemical Vapor Deposition (MOCVD) process.
27 . The method of claim 25 , wherein the etch selective material comprises one of InGaAlAs and another Al containing quaternary semiconductor material selected from InP-based semiconductor materials.
28 . The transistor of claim 1 wherein the semiconductor layers comprise layers included in the table:
Description
Material
Emitter metal
Ti/Pt/Au
Cap
In(x)Ga(1-x)As
Emitter
InP
Emitter
In(1-x)A1(x)P
Emitter etch
AlInGaAs or other (Al-Q)
selective layer
Emitter/ledge
In(1-x)Al(x)P
Base
GaAs(x)Sb(1-x)
Collector
InP
Sub-collector
InP
Sub-collector
In(x)Ga(1-x)As
Sub-collector
InP
Etch stop
In(x)Ga(1-x)As
Substrate
InP (SI)
wherein Al-Q comprises Al containing quaternary semiconductor material selected from InP-based semiconductor materials.