EMBEDDED COOLING ASSEMBLIES FOR ADVANCED DEVICE PACKAGING AND METHODS OF MANUFACTURING THE SAME
A device package comprises a package substrate, an integrated cooling assembly disposed on the package substrate, and a material layer disposed over and at least partially encapsulating the integrated cooling assembly. The integrated cooling assembly comprises a semiconductor device and a cold plate attached to the semiconductor device. The cold plate comprises a patterned first side and an opposite second side. The patterned first side comprises a base surface and sidewalls extending downwardly from the base surface. The base surface is spaced apart from the semiconductor device to collectively define a coolant channel therebetween. The coolant channel is in fluid communication with openings disposed through portions of the material layer.
1 . (canceled)
2 . A device package comprising:
a package substrate;
an integrated cooling assembly disposed on the package substrate, the integrated cooling assembly comprising a semiconductor device and a cold plate attached to the semiconductor device; and
a material layer disposed over and at least partially encapsulating the integrated cooling assembly, wherein:
the cold plate comprises a patterned first side and an opposite second side;
the patterned first side comprises a base surface and sidewalls extending downwardly from the base surface;
the base surface is spaced apart from the semiconductor device to collectively define a coolant channel therebetween; and
the coolant channel is in fluid communication with openings disposed through portions of the material layer.
3 . The device package of claim 2 , wherein the cold plate is attached to the semiconductor device by direct dielectric bonds.
4 . The device package of claim 2 , wherein the cold plate is attached to the semiconductor device by direct hybrid bonds.
5 . The device package of claim 2 , further comprising a coolant fluid disposed in the coolant channel.
6 . The device package of claim 2 , wherein openings in the integrated cooling assembly comprise portions of a fluid path that further comprises the openings disposed through the material layer and the coolant channel.
7 . The device package of claim 6 , wherein the openings in the integrated cooling assembly extend between the first side and the second side of the cold plate.
8 . The device package of claim 6 , wherein the openings in the integrated cooling assembly comprise gaps between the first side of the cold plate and the semiconductor device.
9 . The device package of claim 6 , wherein the first side of the cold plate further comprises a plurality of protruding features that extend downwardly from the base surface to disrupt at least portions of a fluid flow path through the coolant channel.
10 . The device package of claim 9 , wherein the plurality of protruding features are directly bonded to the semiconductor device.
11 . The device package of claim 8 , wherein the gaps are disposed at opposite ends of the base surface.
12 . The device package of claim 2 , further comprising a package cover disposed on the material layer.
13 . The device package of claim 12 , wherein the package cover comprises one or more coolant line attachment features.
14 . The device package of claim 2 , further comprising an underfill layer that at least partially encapsulates the integrated cooling assembly in regions outside of the coolant channel.
15 . The device package of claim 12 , wherein the material layer forms an impermeable barrier between the package cover and the cold plate.
16 . The device package of claim 2 , wherein side surfaces of the cold plate and the semiconductor device are substantially flush with one another.
17 . The device package of claim 2 , wherein:
the semiconductor device is a first semiconductor device and the integrated cooling assembly further comprises a plurality of second semiconductor devices vertically arranged in a device stack; and
the device stack is attached to the first side of the cold plate in a side-by-side arrangement with the first semiconductor device.
18 . The device package of claim 17 , wherein the cold plate is attached to a second semiconductor device of the plurality of second semiconductor devices by direct dielectric bonds.
19 . The device package of claim 17 , wherein the cold plate is attached to a second semiconductor device of the plurality of second semiconductor devices by direct hybrid bonds.
20 . The device package of claim 2 , wherein the material layer comprises one or more features extending upwardly to surround each of openings in the integrated cooling assembly, wherein the features provide for connection of coolant lines directly to the material layer.
21 . A method of manufacturing the device package of claim 2 , the method comprising:
directly bonding a first substrate comprising the semiconductor device to a second substrate comprising the cold plate;
singulating the integrated cooling assembly comprising the semiconductor device and the cold plate from the bonded first and second substrates, the cold plate comprising the first side directly bonded to the semiconductor device and the second side opposite the first side, wherein one or more surfaces of the first side are spaced apart from the semiconductor device to define the coolant channel therebetween;
sealingly attaching the material layer to the second side; and
forming openings in the material layer to fluidly connect the openings to the coolant channel.