IP Library › Patent Application 61485177
Patent Application Provisional Small
App. No. 61/485,177 · Confirmation No. 4392

Logic verification module apparatus to serve as a hyper prototype for debugging an electronic design that exceeds the capacity of a single FPGA

Inventor: Mon-Ren Chene
Provisional Application Expired
⬇ PDF
 Code Description Pages PDF
2011-05-20 APP.FILE.REC Filing Receipt 3 View
2011-05-12 ADS Application Data Sheet 4 View
2011-05-12 DRW Drawings-only black and white line drawings 3 View
2011-05-12 SPEC Specification 24 View
2011-05-12 CLM Claims 5 View
2011-05-12 ABST Abstract 1 View
2011-05-12 WFEE Fee Worksheet (SB06) 2 View
2011-05-12 N417 Electronic Filing System Acknowledgment Receipt 3 View
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Quick Facts
App. No.
61/485,177
Filed
2011-05-12