Gate driver, organic light emitting display device including the same, and method for operating the same
A gate driver has a plurality of stages for outputting a gate signal for image at a time of display driving and outputting a gate signal for sensing at a time of sensing driving that follows the display driving. Each of the stages includes a pixel line selecting unit charging an M node with a first preceding stage carry signal according to a pixel line selection signal of a gate-on voltage during the display driving and charging a Q node with a first high-potential power supply voltage according to a sensing start signal of a gate-on voltage and a charged voltage of the M node during the sensing driving, and an output unit outputting a scan clock of a gate-on voltage as the gate signal for sensing while the Q node maintains a charged state on the sensing driving, wherein the first high-potential power supply voltage is higher at the time of the sensing driving than at the time of the display driving.
1 . A gate driver, comprising:
a plurality of stages for outputting a gate signal for an image at a time of display driving, and outputting a gate signal for sensing at a time of sensing driving that follows the display driving, each of the plurality of stages including:
a first input terminal configured to receive a first high-potential power supply voltage having a first voltage level and a second voltage level;
a pixel line selecting unit configured to charge a first node with a first preceding stage carry signal based on a pixel line selection signal for a gate-on voltage during the display driving, and to charge a second node with the first voltage level of the first high-potential power supply voltage based on a sensing start signal for the gate-on voltage and a charged voltage of the first node during the sensing driving; and
an output unit configured to output a scan clock for the gate-on voltage as the gate signal for sensing while the second node maintains a charged state on the sensing driving,
wherein the first voltage level of the first high-potential power supply voltage is received at the first input terminal during the sensing driving, and the second voltage level of the first high-potential power supply voltage is received at the first input terminal during the display driving, and
wherein the first voltage level is higher than the second voltage level.
2 . The gate driver of claim 1 , wherein the first voltage level of the first high-potential power supply voltage is lower than a break-down voltage of transistors electrically connected to the first input terminal.
3 . The gate driver of claim 1 , wherein each of the plurality of stages further includes:
an inverter unit configured to cut off electrical connection between a second input terminal that receives a second high-potential power supply voltage and a third node while the second node maintains the charged state on the sensing driving,
wherein the first voltage level of the first high-potential power supply voltage is higher than the second high-potential power supply voltage, and
wherein the second voltage level of the first high-potential power supply voltage is equal to or substantially equal to the second high-potential power supply voltage.
4 . The gate driver of claim 3 , wherein the second high-potential power supply voltage is the same at the times of the display driving and the sensing driving.
5 . The gate driver of claim 3 , wherein the pixel line selecting unit includes:
a first transistor;
a second transistor, the first transistor and the second transistor electrically connected in series between an input terminal that receives the first preceding stage carry signal and the first node, the first transistor and the second transistor configured to be concurrently turned on based on the pixel line selection signal;
a third transistor having a first electrode electrically connected to the first input terminal and a second electrode electrically connected between the first transistor and the second transistor, the third transistor configured to be turned on based on the charged voltage of the first node;
a fourth transistor having a first electrode electrically connected to the first input terminal, the fourth transistor configured to be turned on based on the charged voltage of the first node; and
a fifth transistor having a first electrode electrically connected to a second electrode of the fourth transistor, and a second electrode electrically connected to the second node, the fifth transistor configured to be turned on based on the sensing start signal.
6 . The gate driver of claim 5 , wherein the pixel line selecting unit further includes:
a sixth transistor having a first electrode electrically connected to the second node, and a second electrode electrically connected to an input terminal that receives a low-potential power supply voltage, the sixth transistor configured to be turned on based on the sensing end signal of the gate-on voltage.
7 . The gate driver of one of claim 3 , wherein the inverter unit is configured to:
discharge the third node to a low-potential power supply voltage based on a second preceding stage carry signal having a phase of a gate-on voltage ahead of that of the first preceding stage carry signal during the display driving,
discharge the third node to the low-potential power supply voltage based on a charged voltage of the second node during the display driving,
charge the third node with the second high-potential power supply voltage according to a discharged voltage of the second node during the display driving,
discharge the third node to the low-potential power supply voltage based on the sensing start signal and the charged voltage of the first node during the sensing driving, and
discharge the third node to the low-potential power supply voltage based on the charged voltage of the second node during the sensing driving.
8 . The gate driver of claim 7 , wherein the inverter unit includes:
a first transistor having a first electrode electrically connected to the second input terminal, and a second electrode electrically connected to the third node;
a second transistor having a first electrode and a gate electrode electrically connected to the second input terminal, and a second electrode electrically connected to a gate electrode of the first transistor;
a third transistor having a first electrode electrically connected to the gate electrode of the first transistor, a second electrode electrically connected to the input terminal that receives the low-potential power supply voltage, and a gate electrode electrically connected to the second node;
a fourth transistor having a first electrode electrically connected to the third node, and a second electrode electrically connected to the input terminal that receives the low-potential power supply voltage, and a gate electrode electrically connected to the second node;
a fifth transistor having a first electrode electrically connected to the third node, a second electrode electrically connected to the input terminal that receives the low-potential power supply voltage, and a gate electrode to which the second preceding stage carry signal of the gate-on voltage is applied;
a sixth transistor having a first electrode electrically connected to the third node, and a gate electrode to which the sensing start signal is applied; and
a seventh transistor having a first electrode electrically connected to a second electrode of the sixth transistor, and a second electrode electrically connected to the input terminal that receives the low-potential power supply voltage and a gate electrode electrically connected to the first node.
9 . An organic light emitting display device comprising:
a gate driver including:
a plurality of stages for outputting a gate signal for an image at a time of display driving, and outputting a gate signal for sensing at a time of sensing driving that follows the display driving, each of the plurality of stages including:
a first input terminal configured to receive a first high-potential power supply voltage having a first voltage level and a second voltage level;
a pixel line selecting unit configured to charge a first node with a first preceding stage carry signal based on a pixel line selection signal for a gate-on voltage during the display driving, and to charge a second node with the first voltage level of the first high-potential power supply voltage based on a sensing start signal for the gate-on voltage and a charged voltage of the first node during the sensing driving; and
an output unit configured to output a scan clock for the gate-on voltage as the gate signal for sensing while the second node maintains a charged state on the sensing driving,
wherein the first voltage level of the first high-potential power supply voltage is received at the input terminal during the sensing driving, and the second voltage level of the first high-potential power supply voltage is received at the input terminal during the display driving,
wherein the first voltage level is higher than the second voltage level; and
a plurality of pixels electrically connected to the gate driver through gate lines, and driven based on the gate signal for the image and the gate signal for sensing.
10 . A method for operating a gate driver including a plurality of stages for outputting a gate signal for an image at a time of display driving, and outputting a gate signal for sensing at a time of sensing driving that follows the display driving, the method comprising:
receiving a first high-potential power supply voltage having a first voltage level and a second voltage level at a first input terminal;
operating a pixel line selecting unit to charge a first node with a first preceding stage carry signal based on a pixel line selection signal for a gate-on voltage during the display driving, and to charge a second node with the first voltage level of the first high-potential power supply voltage based on a sensing start signal for the gate-on voltage and a charged voltage of the first node during the sensing driving; and
operating an output unit to output a scan clock for a gate-on voltage as the gate signal for sensing while the second node maintains a charged state on the sensing driving,
wherein the first voltage level of the first high-potential power supply voltage is received at the input terminal during the sensing driving, and the second voltage level of the first high-potential power supply voltage is received at the input terminal during the display driving,
wherein the first voltage level is higher than the second voltage level.
11 . The method of claim 10 , wherein the first voltage level of the first high-potential power supply voltage is lower than a break-down voltage of transistors electrically connected to the first input terminal.
12 . The method of claim 10 , wherein each of the plurality of stages further includes:
operating an inverter unit to cut off electrical connection between a second input terminal that receives a second high-potential power supply voltage and a third node while the second node maintains the charged state on the sensing driving,
wherein the first voltage level of the first high-potential power supply voltage is higher than the second high-potential power supply voltage, and
wherein the second voltage level of the first high-potential power supply voltage is equal to or substantially equal to the second high-potential power supply voltage.
13 . The method of claim 12 , wherein the second high-potential power supply voltage is the same at the times of the display driving and the sensing driving.
14 . The method of claim 13 , wherein a gate-on voltage interval of the first preceding stage carry signal and a gate-on voltage interval of the pixel line selection signal are identical to each other.
15 . The method of claim 14 , wherein the inverter unit
discharges the third node to a low-potential power supply voltage based on a second preceding stage carry signal having a phase of a gate-on voltage ahead of that of the first preceding stage carry signal during the display driving,
discharges the third node to the low-potential power supply voltage based on a charged voltage of the second node during the display driving,
charges the third node with the second high-potential power supply voltage based on a discharged voltage of the second node during the display driving,
discharges the third node to the low-potential power supply voltage based on the sensing start signal and the charged voltage of the M node during the sensing driving, and
discharges the third node to the low-potential power supply voltage based on the charged voltage of the second node during the sensing driving.
16. A gate driver having a plurality of stages, each of the plurality of stages comprising:
a pixel line selecting circuit having a first input terminal configured to receive a first high-potential power supply voltage having a first voltage level and a second voltage level;
an output circuit configured to output a first gate signal for an image during display driving and to output a second gate signal for sensing during sensing driving,
wherein the first voltage level of the first high-potential power supply voltage is received at the first input terminal during the sensing driving and the second voltage level of the first high-potential power supply voltage is received at the first input terminal during the display driving, and
wherein the first voltage level is higher than the second voltage level.
17. The gate driver of claim 16 , wherein the first voltage level of the first high-potential power supply voltage is lower than a break-down voltage of transistors connected to the first input terminal.
18. The gate driver of claim 16 , wherein the pixel line selecting circuit charges a first node with a first preceding stage carry signal based at least in part on a pixel line selection signal for a gate-on voltage during the display driving, and charges a second node to a charged state with the first voltage level of the first high-potential power supply voltage based at least in part on a sensing start signal for the gate-on voltage and a charged voltage of the first node during the sensing driving.
19. The gate driver of claim 18 , wherein each of the plurality of stages further includes:
an inverter circuit including a second input terminal and configured to cut off electrical connection between the second input terminal that receives a second high-potential power supply voltage and a third node while the second node maintains the charged state on the sensing driving.
20. The gate driver of claim 19 , wherein at least part of the first high-potential power supply voltage is different from at least part of the second high-potential power supply voltage.
21. The gate driver of claim 19 , wherein the first voltage level of the first high-potential power supply voltage is higher than the second high-potential power supply voltage, and
wherein the second voltage level of the first high-potential power supply voltage is equal to the second high-potential power supply voltage.
22. The gate driver of claim 19 , wherein the second high-potential power supply voltage is the same during both the display driving and the sensing driving.
23. The gate driver of claim 18 , wherein the pixel line selecting circuit includes:
a first transistor;
a second transistor, the first transistor and the second transistor connected in series between a third input terminal that receives the first preceding stage carry signal and the first node, the first transistor and the second transistor configured to be concurrently turned on based at least in part on the pixel line selection signal;
a third transistor having a first electrode connected to the first input terminal and a second electrode connected between the first transistor and the second transistor, the third transistor configured to be turned on based at least in part on the charged voltage of the first node;
a fourth transistor having a first electrode connected to the first input terminal, the fourth transistor configured to be turned on based at least in part on the charged voltage of the first node;
a fifth transistor having a first electrode connected to a second electrode of the fourth transistor, and a second electrode connected to the second node, the fifth transistor configured to be turned on based at least in part on the sensing start signal,
a sixth transistor having a first electrode connected to the second node, and a second electrode connected to a fourth input terminal that receives a low-potential power supply voltage, the sixth transistor configured to be turned on based at least in part on a sensing end signal of the gate-on voltage, and
a first capacitor connected to the first input terminal and the first node.
24. The gate driver of claim 23 wherein the first transistor is directly connected to the third terminal and the first and second transistor are directly connected in series to each other.
25. The gate driver of claim 23 wherein the second electrode of the third transistor is directly connected at a fourth node between the first transistor and the second transistor.
26. The gate driver of claim 19 , wherein the inverter circuit is configured to:
discharge the third node to a low-potential power supply voltage based at least in part on a second preceding state carry signal having a phase of a gate-on voltage ahead of that of the first preceding stage carry signal during the display driving,
discharge the third node to the low-potential power supply voltage based at least in part on a charged voltage of the second node during the display driving,
charge the third node with the second high-potential power supply voltage according to a discharged voltage of the second node during the display driving,
discharge the third node to the low-potential power supply voltage based at least in part on the sensing start signal and the charged voltage of the first node during the sensing driving, and
discharge the third node to the low-potential power supply voltage based at least in part on the charged voltage of the second node during the sensing driving.
27. The gate driver of claim 26 , wherein the inverter circuit includes:
a first transistor having a first electrode connected to the second input terminal, and a second electrode connected to the third node;
a second transistor having a first electrode and a gate electrode connected to the second input terminal, and a second electrode connected to a gate electrode of the first transistor;
a third transistor having a first electrode connected to the gate electrode of the first transistor, a second electrode connected to the input terminal that receives the low-potential power supply voltage, and a gate electrode connected to the second node;
a fourth transistor having a first electrode connected to the third node, and a second electrode connected to the input terminal that receives the low-potential power supply voltage, and a gate electrode connected to the second node;
a fifth transistor having a first electrode connected to the third node, a second electrode connected to the input terminal that receives the low-potential power supply voltage, and a gate electrode to which the second preceding stage carry signal of the gate-on voltage is applied;
a sixth transistor having a first electrode connected to the third node, and a gate electrode to which the sensing start signal is applied; and
a seventh transistor having a first electrode connected to a second electrode of the sixth transistor, and a second electrode connected to the input terminal that receives the low-potential power supply voltage and a gate electrode connected to the first node.
28. The gate driver of claim 27 wherein the first electrode and the gate electrode of the second transistor are directly connected to the second input terminal.
29. The gate driver of claim 27 wherein the second electrode of the second transistor is directly connected to the gate electrode of the first transistor.
30. The gate driver of claim 18 , wherein the output circuit includes:
a first output node configured to output a current stage carry signal having a phase of a gate-on voltage later than that of the first preceding stage carry signal;
a first output transistor having a first electrode connected to a first clock input terminal that receives a carry clock for the gate-on voltage as the current stage carry signal, and a second electrode connected to the first output node;
a second output node configured to output the first gate signal;
a second output transistor having a first electrode connected to a second clock input terminal that receives a scan clock for the gate-on voltage as the first gate signal, and a second electrode connected to the second output node,
wherein a gate electrode of the first output transistor and a gate electrode of the second output transistor are connected to the second node.
31. The gate driver of claim 30 , wherein the second output node configured to alternatively output the second gate signal.
32. The gate driver of claim 30 wherein the second output transistor has a first electrode connectable a second clock input terminal that receives a scan clock for the gate-on voltage as the second gate signal, and a second electrode connected to the second output node.
33. The gate driver of claim 30 , wherein the output circuit further includes a second capacitor connected to the second node and the second output node.
34. The gate driver of claim 1 , wherein the each of the plurality of stages includes a plurality of transistors, and
wherein at least one of the transistors includes an oxide semiconductor layer.
35. The gate driver of claim 16 , wherein the first input terminal is part of the pixel line selecting circuit.
36. A gate driver having a plurality of stages, each of the plurality of stages comprising:
a pixel line selecting circuit including a first node and a second node;
a first input terminal configured to receive da first high-potential power supply voltage having a first voltage level and a second voltage level; and
an inverter circuit including a second input terminal and a third node, the inverter circuit configured to cut off electrical connection between the second input terminal that receives a second high-potential power supply voltage and the third node while the second node maintains a charged state on the sensing driving,
wherein the first voltage level of the first high-potential power supply voltage is received at the first input terminal during the sensing driving, and the second voltage level of the first high-potential power supply voltage is received at the first input terminal during the display driving,
wherein a third voltage level of the second high-potential power supply voltage is received at the second input terminal during the sensing driving, and a fourth voltage level of the second high-potential power supply voltage is received at the second input terminal during the display driving, and
wherein the first voltage level is higher than the second voltage level.
37. The gate driver of claim 36 , wherein the first voltage level is different from the third voltage level during the sensing driving, and
wherein the second voltage level is the same as the fourth voltage level during the display driving.
38. The gate driver of claim 36 , wherein the first voltage level is higher than the third voltage level at the time of the sensing driving, and
wherein the second voltage level is the same as the fourth voltage level at the time of the display driving.
39. An organic light emitting display device comprising:
a data driver;
a gate driver having a plurality of stages; and
a plurality of pixels connected to the data driver through data lines and reference lines, the pixels being connected to the gate driver through gate lines,
wherein at least one of the plurality of stages includes:
a pixel line selecting circuit having a first input terminal configured to receive a first high-potential power supply voltage having a first voltage level and a second voltage level;
an output circuit configured to output a first gate signal for an image during display driving and to output a second gate signal for sensing during sensing driving that follows the display driving,
wherein the first voltage level of the first high-potential power supply voltage is received at the first input terminal during the sensing driving, and the second voltage level of the first high-potential power supply voltage is received at the first input terminal during the display driving, and
wherein the first voltage level is higher than the second voltage level.
40. The organic light emitting display device of claim 39 , wherein the each of the plurality of stages includes a plurality of transistors, and
wherein at least one of the transistors includes an oxide semiconductor layer.
41. The organic light emitting display device of claim 39 , wherein each of the plurality of pixels includes:
a driving transistor having a first electrode connected to a high-potential pixel voltage, a second electrode connected a source node and a gate electrode connected to a gate node;
a first switching transistor having a first electrode connected to one of the data lines, a second electrode connected the gate node, and a gate electrode connected to one of the gate lines;
a second switching transistor having a first electrode connected to the source node, a second electrode connected to one of the reference lines, and a gate electrode connected to one of the gate lines;
an organic light emitting having a first electrode connected to the source node, and a second electrode connected to a low-potential pixel voltage, and
a storage capacitor having a first electrode connected to the gate node, and a second electrode connected to the source node.
42. The organic light emitting display device of claim 19 , wherein at least one of the first and second switching transistors includes an oxide semiconductor layer.
43. A gate driver, comprising:
a plurality of stages for outputting a gate signal for an image during display driving and outputting a gate signal for sensing during sensing driving, each of the plurality of stages including:
a first input terminal configured to receive a first high-potential power supply voltage having a first voltage level and a second voltage level;
a pixel line selecting circuit configured to charge a first node with a first preceding stage carry signal; and
an output unit configured to output a scan clock for the gate-on voltage,
wherein the first voltage level of the first high-potential power supply voltage is received at the first input terminal during the sensing driving, and the second voltage level of the first high-potential power supply voltage is received at the first input terminal during the display driving, and
wherein the first voltage level is higher than the second voltage level.
44. The gate driver of claim 43 wherein the pixel line selecting circuit is configured to charge the first node with the first preceding stage carry signal based on a pixel line selection signal for a gate-on voltage during the display driving.
45. The gate driver of claim 43 wherein the pixel line selecting circuit is configured to charge the second node with the first voltage level of the first high-potential power supply voltage based on a sensing start signal for the gate-on voltage and a charged voltage of the first node during the sensing driving.