Simplified gate driver configuration and display device including the same
Disclosed herein is a gate driver including a plurality of stages. The nth stage of the plurality of stages includes a first scan signal output unit configured to output the kth clock as a first scan signal through a first scan signal output node when a voltage of a Q-node is at a high state, and an emission control signal output unit configured to output a gate high voltage through an emission control signal output node when a voltage of the first scan signal output node and a voltage of an EQ-node are at the high state by an emission control clock. The emission control signal output unit is electrically connected to the Q-node. The gate driver includes a scan signal output and an emission control signal output, so that GIPs having the same configuration can be disposed on the left and right sides of a display panel.
1. A gate driver including a plurality of stages having an nth stage, the n th stage comprising:
a first circuit configured to output a k th clock as a first scan signal through a first scan signal output node when a voltage of a Q-node is at a high state and a voltage of a QB-node is at low state; and
an emission circuit configured to output a gate high voltage (VGH) through an emission control signal output node if (1) a voltage of the first scan signal output node is at the high state and (2) a voltage of an EQ-node is at the high state by an emission control clock (where n and k are positive integers),
wherein the emission circuit is electrically connected to the Q-node; and
wherein the emission circuit includes an emission control logic circuit and an emission control buffer, the emission control logic circuit including:
a first emission control switching element having a gate electrode connected to the first scan signal output node and disposed between an emission control clock line for applying the emission control clock and the EQ-node;
a second emission control switching element having a gate electrode connected to the first scan signal output node and disposed between an emission control reset signal line for applying an emission control reset signal and the EQB-node; and
a third capacitor disposed between the EQ-node and the emission control signal output node.
2. The gate driver of claim 1 , wherein the emission control buffer comprises:
an emission control pull-up switching element having a gate electrode connected to the EQ-node and connected to a gate high voltage line for applying the gate high voltage; and
an emission control pull-down switching element having a gate electrode connected to an EQB-node and disposed between a gate low voltage line for applying a gate low voltage and the emission control signal output node.
3. The gate driver of claim 1 , wherein the first circuit includes a first logic circuit and a first buffer.
4. The gate driver of claim 3 , wherein the first buffer comprises:
a first pull-up switching element having a gate electrode connected to the Q-node and disposed between a k th clock line for applying the k th clock and the first scan signal output node; and
a first pull-down switching element having a gate electrode connected to the QB-node and disposed between a gate low voltage line for applying a gate low voltage (VGL) and the first scan signal output node.
5. The gate driver of claim 4 , wherein a voltage of the first scan signal output node is configured to control operation of the emission circuit, and the first logic circuit outputs the voltage of the Q-node and the voltage of the QB-node, so that they are opposite to each other.
6. The gate driver of claim 4 , wherein the first logic circuit comprises:
a first switching element having a gate electrode to receive a first start voltage and connected to a gate high voltage line for applying the gate high voltage;
a second switching element having a gate electrode to receive a (k+3) th clock and connected to the Q-node;
a third switching element having a gate electrode connected to the QB-node and disposed between the gate low voltage line and the second switching element;
a fourth switching element having a gate electrode to receive a (k+2) th clock and connected to the gate high voltage line;
a fifth switching element having a gate electrode to receive the first start voltage and disposed between the gate low voltage line and the fourth switching element; and
a sixth switching element having a gate electrode connected to the Q-node and disposed between the QB-node and the gate low voltage line; and a first capacitor disposed between the Q-node and the first scan signal output node,
wherein an emission control signal output block is electrically connected to the first circuit through the Q-node and the QB-node.
7. The gate driver of claim 1 , further comprising a second circuit electrically connected to the Q-node and configured to output a second scan signal having a phase difference from the first scan signal.
8. The gate driver of claim 7 , wherein the second circuit comprises:
a second pull-up switching element having a gate electrode connected to the Q-node and disposed between a fifth clock line for applying a fifth clock and the second scan signal output node; and
a second pull-down switching element having a gate electrode connected to the QB-node and disposed between a gate low voltage line for applying a gate low voltage and the second scan signal output node.
9. The gate driver of claim 8 , wherein the emission circuit is connected in parallel with the first circuit and the second circuit at the Q-node and the QB-node.
10. A display device comprising:
a display panel including a plurality of pixels; and
a gate driver disposed in the display panel and configured to apply gate signals through gate lines connected to each of the plurality of pixels, wherein the gate driver comprises,
a first circuit configured to output a k th clock as a first scan signal through a first scan signal output node between a pull-up switching element having a gate electrode connected to a Q-node and a pull-down switching element having a gate electrode connected to a QB-node; and
an emission circuit configured to output a gate high voltage synchronized to an emission control clock through an emission control signal output node between an emission control pull-up switching element having a gate electrode connected to an EQ-node and an emission control pull-down switching element having a gate electrode connected to an EQB-node,
wherein the emission circuit is connected in parallel to the first circuit at the Q-node and the QB-node; and
wherein the emission circuit includes an emission control logic circuit and an emission control buffer, the emission control logic circuit including:
a first emission control switching element having a gate electrode connected to the first scan signal output node and disposed between an emission control clock line for applying the emission control clock and the EQ-node;
a second emission control switching element having a gate electrode connected to the first scan signal output node and disposed between an emission control reset signal line for applying an emission control reset signal and the EQB-node; and
a third capacitor disposed between the EQ-node and the emission control signal output node.
11. The display device of claim 10 , wherein the gate driver further comprises a second circuit electrically connected to the Q-node and configured to output a second scan signal having a phase difference with the first scan signal.
12. The display device of claim 11 , wherein the second circuit comprises:
a second pull-up switching element having a gate electrode connected to the Q-node and disposed between a fifth clock line for applying a fifth clock and the second scan signal output node; and
a second pull-up switching element having a gate electrode connected to the QB-node and disposed between a gate low voltage line for applying a gate low voltage and the second scan signal output node.
13. The display device of claim 12 , wherein the emission circuit is connected in parallel with the first circuit and the second circuit at the Q-node and the QB-node.