IP Library › Granted Patent US 6,849,500
Granted Patent B2
US 6,849,500 · App. 10/377,016 · Granted Feb 1, 2005

Method for manufacturing a nonvolatile memory device including an opening formed into an inverse-tapered shape

Assignee: Seiko Epson Corporation
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Quick Facts
Patent No.
US 6,849,500
App. No.
10/377,016
Granted
Feb 1, 2005
Kind
B2
Abstract

A method, for manufacturing a nonvolatile memory device, includes: forming a first insulating layer above a semiconductor layer; forming a first conductive layer above the first insulating layer: forming a stopper layer above the first conductive layer; patterning the stopper layer and the first conductive layer; forming an ONO film made of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer above the semiconductor layer and on both side surfaces of the first conductive layer; forming a second conductive layer above the ONO film; applying anisotropic etching to the second conductive layer, and thereby forming a side wall-like control gate aside each of both side surfaces of the first conductive layer, the ONO film being interposed therebetween; forming an impurity layer to be a source region or a drain region inside of the semiconductor layer; forming a second insulating layer over an entire surface; polishing the second insulating layer so as to expose the stopper layer; removing the stopper layer; forming, on the entire surface, a third conductive layer made of a laminate film of a titanium layer and a titanium nitride layer; patterning the third conductive layer and thereby forming a word line; and patterning the first conductive layer and thereby forming a word gate.

Claims (16)

1. A method for manufacturing a nonvolatile memory device, the method comprising:

forming a first insulating layer above a semiconductor layer;

forming a first conductive layer above the first insulating layer;

forming a stopper layer above the first conductive layer;

patterning the stopper layer and the first conductive layer;

forming an ONO film made of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer above the semiconductor layer and on both side surfaces of the first conductive layer;

forming a second conductive layer above the ONO film;

applying anisotropic etching to the second conductive layer, and thereby forming a side wall control gate aside each of both side surfaces of the first conductive layer, the ONO film being interposed therebetween;

forming an impurity layer to be a source region or a drain region inside of the semiconductor layer;

forming a second insulating layer above an entire surface of the semiconductor layer;

polishing the second insulating layer so as to expose the stopper layer;

removing the stopper layer;

forming, on the entire surface, a third conductive layer made of a laminate film of a titanium layer and a titanium nitride layer;

patterning the third conductive layer and thereby forming a word line; and

patterning the first conductive layer and thereby forming a word gate;

wherein an opening is formed in the second insulating layer by removing the stopper layer, an upper portion of the opening of the second insulating layer is subjected to reverse sputter, and thereby the opening is formed into an inverse-tapered shape.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2003
From: KATO, AIKO; SHIBATA, TAKUMI
To: SEIKO EPSON CORPORATION
Reel/Frame 014222/0409 →
Priority Claims (1)
JP 2002-055982 · Mar 1, 2002 · national
Continuity (1)
Related Publication 20030219944A1 · Nov 27, 2003