Semiconductor package with heat sink attached to substrate
View Patent ↗A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a flange in contact with the substrate, allowing a plurality of clip members to clamp the flange of the heat sink and the substrate. Each of the clip members has a recess portion for receiving the flange of the heat sink and the substrate to thereby firmly position the heat sink on the substrate. The clip members are engaged with edges of the heat sink and the substrate, thereby not affecting trace routability on the substrate. Moreover, the heat sink is mounted on the substrate and would not be dislocated.
1. A semiconductor package with a heat sink, comprising:
a substrate having an upper surface and a lower surface opposed to the upper surfaces, wherein an edge of the substrate is formed with a plurality of grooves penetrating through the upper and lower surfaces of the substrate;
at least one chip mounted on the upper surface of the substrate and electrically connected to the substrate by a plurality of conductive elements;
a heat sink mounted on the upper surface of the substrate and covering the chip, the heat sink having a flat portion and a support portion extending from an edge of the flat portion to the substrate, making the flat portion elevated above the chip by the support portion, wherein the support portion is formed with a flange in contact with the upper surface of the substrate;
a plurality of clip members each having a recess portion for receiving the flange of the heat sink and the substrate, and the flange of the heat sink and the substrate are clamped by the clip members such that a death of each of the grooves is larger than a thickness of each of the clip members, so as to firmly position the heat sink on the substrate; and
a plurality of solder balls implanted on the lower surface of the substrate.
2. The semiconductor package of claim 1 , further comprising: at least one passive component mounted on the upper surface of the substrate at area free of the chip and covered by the heat sink.
3. The semiconductor package of claim 1 , wherein the grooves are situated at positions corresponding to space between adjacent solder balls.
4. The semiconductor package of claim 3 , wherein a width of the groove is smaller than a distance between adjacent solder balls.
5. The semiconductor package of claim 1 , wherein an edge of the flange of the heat sink is formed with a plurality of grooves corresponding in position to the grooves of the substrate, allowing the clip members to be engaged with the corresponding grooves of the heat sink and of the substrate to clamp the heat sink and the substrate.
6. The semiconductor package of claim 5 , wherein the edge of the flange of the heat sink is flush with the edge of the substrate.
7. The semiconductor package of claim 1 , wherein coverage of the flange of the heat sink is smaller than that of the substrate, allowing the clip members to be engaged with the grooves of the substrate and clamp the heat sink and the substrate.
8. The semiconductor package of claim 7 , wherein an edge of the flange of the heat sink is flush with dead ends of the grooves of the substrate.
9. The semiconductor package of claim 1 , wherein the clip members are made of flexible spring steel.
10. The semiconductor package of claim 1 , wherein thickness of the clip members is 0.3-0.4 mm.
11. The semiconductor package of claim 1 , wherein the heat sink is mounted on the substrate by means of an adhesive.