IP Library › Granted Patent US 6,855,633
Granted Patent B2
US 6,855,633 · App. 10/225,127 · Granted Feb 15, 2005

Method for fabricating semiconductor device

Assignee: Matsushita Electric Industrial Co., Ltd.
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Quick Facts
Patent No.
US 6,855,633
App. No.
10/225,127
Granted
Feb 15, 2005
Kind
B2
Abstract

A mask ( 4 ) for forming active regions is formed on a surface portion of a Si layer ( 2 ) serving as a semiconductor region with a thermal oxide film ( 3 ) interposed therebetween. Dummy sidewalls ( 8 ) are formed over the side surfaces of the mask ( 4 ) for forming active regions. Then, etching is performed by using the mask ( 4 ) for forming active regions and the dummy sidewalls ( 8 ) as a mask to form trenches ( 9 ) each defining the side surfaces of the Si layer ( 2 ). Thereafter, each of the trenches ( 9 ) is filled with a plasma CVD oxide film ( 11 ), which is polished till the dummy sidewalls ( 8 ) are exposed at the surface. By removing the dummy sidewalls ( 8 ), oxidation is performed with the upper-surface edge portions of the Si layer ( 2 ) being exposed. This allows the upper-surface edge portions of the Si layer ( 2 ) to be oxidized without involving the oxidation of the lower-surface edge portions of the Si layer ( 2 ).

Claims (13)

1. A method for fabricating a semiconductor device using a substrate having a substrate insulator layer and a semiconductor layer provided on the substrate insulator layer and formed with an active layer of a semiconductor element, the method comprising the steps of:

(a) forming a mask for forming an active region on a surface portion of the semiconductor layer;

(b) forming a dummy side wall over side surfaces of the mask for forming the active region;

(c) etching the semiconductor layer by using the mask for forming active region and the dummy sidewall as a mask, thereby forming a trench that reaches the substrate insulator layer;

(d) after the step (c), filling the trench with an insulating film for isolation;

(e) after the step (d), removing the dummy sidewall to expose an upper-surface edge portion of the semiconductor layer; and

(f) after the step (e), oxidizing the upper-surface edge portion of the semiconductor layer.

2. The method of claim 1 , wherein the step (d) includes depositing the insulating film for isolation on the substrate, polishing the insulating film for isolation by CMP until a surface of the mask for forming the active region is exposed, and thereby filling the trench with the insulating film for isolation, the method further comprising the step of:

after the step (f), selectively removing the mask for forming the active region.

3. The method of claim 1 or 2 , further comprising the step of:

after the step (c) and prior to the step (d), forming a sidewall oxide film with a thickness of 5 nm or less over the side surfaces of the semiconductor layer exposed in the trench, wherein

the step (f) includes forming an oxide film with a thickness of 25 nm or more by oxidation.

4. The method of claim 1 or 2 , wherein the insulating film for isolation is a laminated film composed of a TEOS film and a plasma CVD oxide film.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2014
From: PANASONIC CORPORATION (FORMERLY MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.)
To: GODO KAISHA IP BRIDGE 1
Reel/Frame 032152/0514 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2002
From: KOTANI, NAOKI
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 013215/0963 →
Priority Claims (1)
JP 2001-256562 · Aug 27, 2001 · national
Continuity (1)
Related Publication 20030040187A1 · Feb 27, 2003