Threshold voltage adjustment for MOS devices
The Vt of an MOS transistor is lowered in response to its load current. In a LDO (low dropout) regulator, lowering the Vt of the pass transistor with load increases the level of drive that can be applied to the pass transistor thus allowing a smaller transistor to be used for the same load.
1. In a low dropout voltage (LDO) regulator having a pass transistor coupled between a power source and a load, the improvement comprising:
a p-n diode coupled between the power source and a reference potential;
a resistor divider coupled in parallel to the p-n diode, an output of the resistor divider being coupled to a back gate of the pass transistor;
a variable current source providing a current flow through the parallel combination of the p-n diode and the resistor divider, the variable current flow being proportional to load current.
2. The LDO regulator of claim 1 wherein the p-n diode is formed in the bulk semiconductor region.
3. The LDO regulator of claim 1 wherein the p-n diode is a diode-connected NPN transistor.
4. The LDO regulator of claim 1 wherein the p-n diode is a diode-connected PNP transistor.
5. The LDO regulator of claim 1 wherein the pass transistor is a PMOS transistor.
6. The LDO regulator of claim 1 wherein the resistor divider ratio is less that one-half.
7. The LDO regulator of claim 1 wherein the resistor divider is formed of doped polysilicon.
8. The LDO regulator of claim 1 wherein the variable current source is a current mirror which mirrors a predetermined portion of the load current.
9. The LDO regulator of claim 1 further comprising a current limiting stage coupled between the parallel combination of the resistor divider and the p-n junction and the reference potential.
10. The LDO regulator of claim 9 wherein the current limiting stage comprises a current mirror limiting current through a sense transistor and current mirror transistor.
11. A low dropout (LDO) regulator comprising:
a differential amplifier having a first input coupled to a voltage reference and a second input coupled to load voltage and generating an error voltage output;
a pass transistor coupled between a power source and the load, the pass transistor having a gate coupled to the error voltage output and being controlled by the error voltage and having a back gate;
a p-n diode coupled between the power source and a reference potential and having a resistor divider coupled in parallel therewith an output of the resistor divider being coupled to the back gate of the pass transistor; and
a first current mirror having a sense transistor coupled in parallel to the pass transistor and conducting a current having a predetermined ratio to the load current, and a mirror transistor in series with the p-n diode.
12. The LDO regulator of claim 11 further comprising a second current mirror coupled between the first current mirror and the reference potential for limiting current flow through the first current mirror.
13. The LDO regulator of claim 11 wherein the pass transistor is a PMOS transistor.
14. The LDO regulator of claim 11 wherein the p-n diode is a diode-connected NPN transistor.
15. The LDO regulator of claim 11 wherein the p-n diode is a diode-connected PNP transistor.
16. A method of controlling the threshold voltage of a MOS transistor having a back gate comprising:
providing a back gate bias circuit comprising a p-n junction coupled in parallel to a resistor divider, an output of the resistor divider being coupled to the back gate, the back gate bias circuit being in parallel to the source-drain path of the MOS transistor; and
generating a current proportional to load current of the MOS transistor and passing the current through the back gate bias circuit.
17. The method of claim 16 wherein generating a current proportional to the load comprises mirroring the current in the load using a current mirror.
18. The method of claim 17 wherein a sense transistor having smaller dimensions than the MOS transistor generates the current for the current mirror.