MISFET
P-type active region 12 ; n-type source/drain regions 13 a and 13 b ; gate insulating film 14 made of a thermal oxide film; gate electrode 15 ; source/drain electrodes 16 a and 16 b , are provided over a p-type SiC substrate 11 . In the active region 12 , p-type heavily doped layers 12 a , which are thin enough to create a quantum effect, and thick undoped layers 12 b are alternately stacked. When carriers flow, scattering of impurity ions in the active region is reduced, and the channel mobility increases. In the OFF state, a depletion layer expands throughout the active region, and the breakdown voltage increases. As a result of reduction in charges trapped in the gate insulating film or near the interface between the gate insulating film and the active region, the channel mobility further increases.
1. A semiconductor device comprising:
a compound semiconductor layer formed on a substrate;
two heavily doped regions, which are defined and spaced apart from each other in the compound semiconductor layer and contain an impurity of a first conductivity type;
a first active region, which is sandwiched between the two heavily doped regions and contains the impurity of the first conductivity type at a concentration lower than in the impurity of the first conductivity type in the two heavily doped regions;
a gate insulating film formed on the active region; and
a gate electrode formed on the gate insulating film,
wherein the first active region comprises a plurality of heavily doped layers containing the impurity of the first conductivity type, and a plurality of semiconductor layers each composed of a lightly doped layer containing the impurity of the first conductivity type at a concentration lower than in the heavily doped layers, or composed of an undoped layer containing no impurity,
the plurality of heavily doped layers and the plurality of semiconductor layers are alternately stacked, and
the plurality of heavily doped layers and the plurality of semiconductor layers are made of SiC.
2. The semiconductor device of claim 1 , wherein the plurality of heavily doped layers each has the same thickness.
3. The semiconductor device of claim 2 , wherein the thickness of the plurality of heavily doped layers is not less than one monolayer to not more than 20 nm.
4. The semiconductor device of claim 1 , wherein the plurality of semiconductor layers each has the same thickness.
5. The semiconductor device of claim 4 , wherein the thickness of the plurality of semiconductor layers is not less than 10 nm to not more than 100 nm.
6. The semiconductor device of claim 1 , wherein the impurity of the first conductivity type is an n-type impurity.
7. The semiconductor device of claim 1 , wherein a carrier concentration continuously changes so that a peak showing a maximum value of the carrier concentration is in the plurality of heavily doped layers and a valley showing a minimum value of the carrier concentration is in the plurality of semiconductor layers.
8. The semiconductor device of claim 1 , wherein carriers exist not only in the plurality of heavily doped layers but also in the plurality of semiconductor layers.
9. The semiconductor device of claim 8 , wherein carriers spread out from the plurality of heavily doped layers to the plurality of semiconductor layers.
10. The semiconductor device of claim 1 , further comprising a second active region, which is sandwiched between the first active region and the gate insulating film and contains the impurity of the second conductivity type,
wherein the second active region comprises a plurality of heavily doped layers containing the impurity of the second conductivity type, and a plurality of semiconductor layers each composed of a lightly doped layer containing the impurity of the second conductivity type at a concentration lower than in the heavily doped layers, or composed of an undoped layer containing no impurity,
the plurality of heavily doped layers and the plurality of semiconductor layers are alternately stacked, and
the plurality of heavily doped layers and the plurality of semiconductor layers are made of SiC.
11. The semiconductor device of claim 10 , wherein the plurality of heavily doped layers each has the same thickness.
12. The semiconductor device of claim 11 , wherein the thickness of the plurality of heavily doped layers is not less than one monolayer to not more than 20 nm.
13. The semiconductor device of claim 10 , wherein the plurality of semiconductor layers each has the same thickness.
14. The semiconductor device of claim 13 , wherein the thickness of the plurality of semiconductor layers is not less than 10 nm to not more than 100 nm.
15. The semiconductor device of claim 10 , wherein the impurity of the first conductivity type is an n-type impurity and the impurity of the second conductivity type is a p-type impurity.
16. The semiconductor device of claim 10 , wherein a carrier concentration continuously changes so that a peak showing a maximum value of the carrier concentration is in the plurality of heavily doped layers and a valley showing a minimum value of the carrier concentration is in the plurality of semiconductor layers.
17. The semiconductor device of claim 10 , wherein carriers exist not only in the plurality of heavily doped layers but also in the plurality of semiconductor layers.
18. The semiconductor device of claim 17 , wherein carriers spread out from the plurality of heavily doped layers to the plurality of semiconductor layers.
19. The semiconductor device of claim 10 , further comprising a third active region, which is sandwiched between the first active region and the gate insulating film and contains the impurity of the second conductivity type,
wherein the third active region comprises a plurality of heavily doped layers containing the impurity of the second conductivity type, and a plurality of semiconductor layers each composed of a lightly doped layer containing the impurity of the second conductivity type at a concentration lower than in the heavily doped layers, or composed of an undoped layer containing no impurity,
the plurality of heavily doped layers and the plurality of semiconductor layers are alternately stacked, and
the plurality of heavily doped layers and the plurality of semiconductor layers are made of SiC.
20. The semiconductor device of claim 19 , wherein the plurality of heavily doped layers each has the same thickness.
21. The semiconductor device of claim 20 , wherein the thickness of the plurality of heavily doped layers is not less than one monolayer to more than 20 nm.
22. The semiconductor device of claim 19 , wherein the plurality of semiconductor layers each has the same thickness.
23. The semiconductor device of claim 22 , wherein the thickness of the plurality of semiconductor layers is not less than 10 nm to not more than 100 nm.
24. The semiconductor device of claim 19 , wherein the impurity of the first conductivity type is an n-type impurity and the impurity of the second conductivity type is a p-type impurity.
25. The semiconductor device of claim 19 , wherein a carrier concentration continuously changes so that a peak showing a maximum value of the carrier concentration is in the plurality of heavily doped layers and a valley showing a minimum value of the carrier concentration is in the plurality of semiconductor layers.
26. The semiconductor device of claim 19 , wherein carriers exist not only in the plurality of heavily doped layers but also in the plurality of semiconductor layers.
27. The semiconductor device of claim 26 , wherein carriers spread out from the plurality of heavily doped layers to the plurality of semiconductor layers.
28. The semiconductor device of claim 19 , wherein the substrate and the compound semiconductor layer are formed as a unit, and
wherein a trench is formed by digging in the compound semiconductor layer, and
wherein the gate insulating film and the gate electrode are formed so as to surround the bottom and the side faces of the trench, and
the one of the two heavily doped layers is defined in the surface part of the compound semiconductor layer and the other is defined in the lowest part of the compound semiconductor layer.
29. The semiconductor device of claim 10 , wherein the substrate and the compound semiconductor layer are formed as a unit, and
wherein a trench is formed by digging in the compound semiconductor layer, and
wherein the gate insulating film and the gate electrode are formed so as to surround the bottom and the side faces of the trench, and
the one of the two heavily doped layers is defined in the surface part of the compound semiconductor layer and the other is defined in the lowest part of the compound semiconductor layer.
30. The semiconductor device of claim 1 , wherein the substrate and the compound semiconductor layer are formed as a unit, and
wherein a trench is formed by digging in the compound semiconductor layer, and
wherein the gate insulating film and the gate electrode are formed so as to surround the bottom and the side faces of the trench, and
the one of the two heavily doped layers is defined in the surface part of the compound semiconductor layer and the other is defined in the lowest part of the compound semiconductor layer.