IP Library › Granted Patent US 6,869,817
Granted Patent B2
US 6,869,817 · App. 10/233,143 · Granted Mar 22, 2005

Image sensor and method of manufacturing the same

Assignee: Hynix Semiconductor Inc.
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Quick Facts
Patent No.
US 6,869,817
App. No.
10/233,143
Granted
Mar 22, 2005
Kind
B2
Abstract

Disclosed is a method of manufacturing an image sensor having light sensitivity over a photodiode equal in area to that of a unit pixel. The image sensor includes an image sensor comprising: a first semiconductor substrate doped with a first conductive dopant; a first diffusion layer formed in the semiconductor substrate and doped with a second conductive dopant; a second diffusion layer formed in the semiconductor substrate adjacent the first diffusion layer and having a width wider than a width of the first diffusion layer; a third diffusion layer doped with the first conductive dopant and formed at an exposed surface of the semiconductor substrate in the first diffusion layer; a gate electrode formed on the exposed surface and having a first edge adjacent to the third diffusion layer; and a fourth diffusion layer doped with the second conductive dopant and formed at the exposed surface adjacent a second edge of the gate electrode, the fourth diffusion layer defining a gap with the second diffusion layer.

Claims (23)

1. A method of manufacturing an image sensor, comprising the steps of:

a) forming a first diffusion layer within a semiconductor substrate, semiconductor substrate being doped of a first conductive dopant and the first diffusion layer being doped of a second conductive dopant;

b) forming a gate electrode on the semiconductor substrate, the gate electrode having a first sidewall and a second sidewall;

c) forming a second diffusion layer in the semiconductor substrate adjacent the first diffusion layer;

d) forming a first spacer at the first sidewall and a second spacer at the second sidewall;

e) forming a third diffusion layer in the second diffusion layer adjacent the first spacer, the third diffusion layer being doped with the first conductive dopant; and

f) forming a fourth diffusion layer within the semiconductor substrate adjacent the second spacer, the fourth diffusion layer being doped with the second conductive dopant,

wherein a part of the first diffusion layer is under the fourth diffusion layer.

2. The method of claim 1 , wherein a dopant concentration of the first diffusion layer is equal to a dopant concentration in the second diffusion layer, a dopant concentration of the third diffusion layer is higher than the dopant concentration of the first diffusion layer and a dopant concentration of the fourth diffusion layer is higher than the dopant concentration of the second diffusion layer.

3. The method of claim 1 , wherein an ion injection energy for forming the first diffusion layer is larger than an ion injection energy for forming the second diffusion layer and an ion injection energy for forming the third diffusion layer is smaller than an ion injection energy for forming the second diffusion layer.

4. The method of claim 1 , wherein the first diffusion layer and the fourth diffusion layer define a gap for preventing a short when the first diffusion layer and the second diffusion layer are depleted.

5. A method of manufacturing an image sensor, comprising the steps of:

a) forming a first diffusion layer within a semiconductor substrate, the semiconductor substrate being doped of a first conductive dopant and the first diffusion layer being doped of a second conductive dopant;

b) forming a gate electrode on the semiconductor substrate, the gate electrode having a first sidewall and a second sidewall;

c) forming a second diffusion layer in the semiconductor substrate adjacent the first diffusion layer;

d) forming a first spacer at the first sidewall and a second spacer at the second sidewall;

e) forming a third diffusion layer in the second diffusion layer adjacent the first spacer, the third diffusion layer being doped with the first conductive dopant;

f) forming a fourth diffusion layer within the semiconductor substrate adjacent the second spacer, the fourth diffusion layer being doped with the second conductive dopant; and

g) forming a fifth diffusion layer between the fourth diffusion layer and the first diffusion layer.

6. The method of claim 5 , wherein the fourth diffusion layer and the fifth diffusion layer are formed by ion injection using the same mask.

7. The method of claim 5 , wherein a dopant concentration of the first diffusion layer is equal to a dopant concentration in the second diffusion layer, a dopant concentration of the third diffusion layer is higher than the dopant concentration of the first diffusion layer, a dopant concentration of the fourth diffusion layer is higher than the dopant concentration of the second diffusion layer, and a dopant concentration of the fifth diffusion layer is higher than the dopant concentration of the second diffusion layer.

8. The method of claim 5 , wherein an ion injection energy for forming the first diffusion layer is larger than an ion injection energy for forming the second diffusion layer and an ion injection energy for forming the third diffusion layer is smaller than an ion injection energy for forming the second diffusion layer.

9. The method of claim 5 , wherein an ion injection energy for forming the fourth diffusion layer is smaller than an ion injection energy for forming the fifth diffusion layer.

Assignments (6)
MERGER Recorded Jul 22, 2011
From: CROSSTEK CAPITAL, LLC
To: INTELLECTUAL VENTURES II LLC
Reel/Frame 026637/0632 →
PARTIAL RELEASE OF SECURITY INTEREST Recorded Aug 10, 2009
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 023075/0054 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: CROSSTEK CAPITAL, LLC
Reel/Frame 022764/0270 →
AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT Recorded Feb 18, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 022277/0133 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2005
From: HYNIX SEMICONDUCTOR, INC.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 016216/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2002
From: HWANG, JOON
To: HYNIX SEMICONDUCTOR, INC.
Reel/Frame 013255/0983 →
Priority Claims (1)
KR 2001-71446 · Nov 16, 2001 · national
Continuity (1)
Related Publication 20030096443A1 · May 22, 2003