Method to solve via poisoning for porous low-k dielectric
View Patent ↗A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.
1. A method to solve via poisoning for insulative porous low-k materials comprising the steps of:
providing a substrate having a first and second insulative layers separated from each other by an intervening etch-stop layer, and having a passivation layer disposed on a side of said first insulative layer opposite from said etch-stop layer;
forming a hole opening in said first and second insulative layers, including said intervening etch-stop layer;
forming a low-k protection layer over said second insulating layer, including in said hole opening, wherein said low-k protection layer prevents outgassing from said first and second insulative layers;
forming a trench opening over said hole opening to form a dual damascene structure;
selectively removing part of said low-k protection layer so as to leave a portion thereof on verticle walls of said hole opening;
removing a portion of said passivation layer at an end of said hole opening remote from said second insulative layer;
forming a barrier layer on the vertical walls of said trench opening and on the portion of said low-k protection layer on the vertical walls of said hole opening;
forming a metal layer on said barrier layer in said dual damascene structure; and
performing chemical mechanical polishing (CMP), to complete the forming of said dual damascene structure.
2. The method of claim 1 , wherein said first insulative layer is a low-k dielectric having a dielectric constant between about 2.0 to 3.0.
3. The method of claim 1 , wherein said first insulative layer has a thickness between about 2000 to 10000 Å.
4. The method of claim 1 , wherein said intervening etch-stop layer is silicon nitride.
5. The method of claim 1 , wherein said intervening etch-stop layer has a thickness between about 50 to 1000 Å.
6. The method of claim 1 , wherein said second insulative layer is a low-k dielectric having a dielectric constant between about 2.0 to 3.0.
7. The method of claim 1 , wherein said second insulative layer has a thickness between about 2000 to 100000 Å.
8. The method of claim 1 , wherein, said low-k protection layer material is selected from the group comprising SiO 2 , SiN, SiC or SiNC.
9. The method of claim 1 , wherein said low-k protection layer has a thickness between about 20 to 1000 Å.
10. The method of claim 1 , wherein said barrier layer material is selected from the group comprising Ta, Ti, TaN, TiSiN, TaSiN, or WN.
11. The method of claim 1 , wherein said barrier layer has a thickness between about 30 to 500 Å.
12. The method of claim 1 , wherein said metal comprises copper.
13. A method to salve via poisoning for insulative porous low-k materials in a dual damascene structure comprising the steps of:
providing a substrate having a passivation layer formed over a first metal layer formed on said substrate;
forming a first insulative layer over said substrate;
forming an etch-stop layer over said first insulative layer;
forming a second insulative layer over said etch-stop layer;
forming a first photoresist layer over said second insulative layer and patterning said photoresist to form a first photoresist mask having a hole pattern;
etching said first and second insulative layers, including said etch-stop layer through said hole pattern to form a hole reaching said passivation layer;
removing said first photoresist mask from said second insulative layer;
forming a low-k protection layer over said substrate on said second insulative layer, including in said hole opening;
forming a second photoresist layer over said substrate, including said hole opening and patterning said second photoresist to form a second photoresist mask having a trench pattern;
etching said second insulative layer through said trench pattern in said second photoresist mask to form a trench in said second insulative layer, thus completing the forming of said dual damascene structure in said substrate;
removing said second photoresist mask;
removing said low-k protection layer from over said substrate and from the bottom of said hole opening and thereby exposing underlying said passivation layer while leaving said low-k protection layer on the vertical sides of said hole opening;
removing said passivation layer from said bottom of said hole opening, thereby exposing underlying said first metal layer;
forming a barrier layer over said substrate, including in said dual damascene structure, wherein said barrier layer conforms to said low-k protective layer in said hole opening and conforms to said trench in said second insulative layer;
depositing a second metal over said barrier layer in said dual damascene structure; and
performing chemical mechanical polishing (CMP) to complete the forming of said dual damascene structure.
14. The method of claim 13 , wherein said substrate is silicon.
15. The method of claim 13 , wherein said passivation layer comprises silicon nitride (SiN).
16. The method of claim 13 , wherein said passivation layer has a thickness between about 30 to 1000 Å.
17. The method of claim 13 , wherein said first insulative layer is a low-k dielectric having a dielectric constant between about 2.0 to 3.0.
18. The method of claim 13 , wherein said first insulative layer has a thickness between about 2000 to 100000 Å.
19. The method of claim 13 , wherein said intervening etch-stop layer is silicon nitride.
20. The method of claim 13 , wherein said intervening etch-stop layer has a thickness between about 30 to 1000 Å.
21. The method of claim 13 , wherein said second insulative layer is a low-k dielectric having a dielectric constant between about 2.0 to 3.0.
22. The method of claim 13 , wherein said second insulative layer has a thickness between about 2000 to 100000 Å.
23. The method of claim 13 , wherein said etching said first and second insulative layers is accomplished with a recipe comprising C 2 F 6 , C 4 F 8 , Ar, N 2 and O 2 .
24. The method of claim 13 , wherein said etching said etch-stop layer is accomplished with a recipe comprising C 2 F 6 , C 4 F 8 , Ar, N 2 and O 2 .
25. The method of claim 13 , wherein said low-k protection layer material is selected from the group comprising SiO 2 , SiN, SiCN or SiC.
26. The method of claim 13 , wherein said low-k protection layer has a thickness between about 30 to 1000 Å.
27. The method of claim 13 , wherein said removing said low-k protection layer is accomplished with a recipe comprising C 2 F 6 , C 4 F 8 , Ar, N 2 and O 2 .
28. The method of claim 13 , wherein said barrier layer material is selected from the group comprising Ta, Ti, TaN, TiSiN, TaSiN, or WN.
29. The method of claim 13 , wherein said barrier layer has a thickness between about 30 to 500 Å.
30. The method of claim 13 , wherein said second metal comprises copper.