Multi-chip module and method for forming and method for deplating defective capacitors
View Patent ↗A method for deplating defective capacitors comprising forming a plurality of capacitors on a semiconductor substrate, forming a plurality of metal contacts on the plurality of capacitors, and depositing a layer of photoresist on the semiconductor substrate. The photoresist layer is patterned so that the plurality of metal contacts are exposed, which are then contacted with an electrically conductive solution. The metal contacts, which are disposed over defective capacitors, are subsequently deplated. A method for forming a multi-chip module comprising forming a thin-film polymeric interconnect structure having a pair of sides, one of which is disposed on a silicon substrate having active or passive devices and the other of which has a computer chip mounted thereon. A multi-chip module formed by the method.
1. A multi-chip module comprising:
a multilayer thin-film polymeric interconnect structure formed on a semiconductor layer, said interconnect structure having a first side and a second side, said second side being adjacent to said semiconductor layer;
a chip disposed on the first side;
wherein said semiconductor layer comprises active or passive devices.
2. The multi-chip module of claim 1 wherein the active devices comprise SRAMs and wherein the passive devices comprise chip capacitors.
3. The multi-chip module of claim 1 wherein the semiconductor layer further comprises an aperture extending through the layer.
4. The multi-chip module of claim 3 wherein the aperture is filled with solder.
5. A multichip module substrate capacitor structure comprising:
a semiconductor substrate having a top surface and a bottom surface;
a doped region of the substrate located at the substrate's top surface;
an ohmic contact located on the top surface of the substrate, and a first dielectric layer disposed over the doped region;
a first conductive layer having a top surface and a bottom surface, and being disposed over the first dielectric layer with its bottom surface adjacent to the first dielectric layer, said first conductive layer having at least a sub-layer of a first conductive material disposed at its top surface;
a second dielectric layer disposed over the first conductive layer;
an aperture formed in the second dielectric layer and disposed over the first conductive layer to expose a portion thereof;
a conductive via formed through the aperture and disposed against a portion of the first conductive layer and comprising a second conductive material disposed adjacent to the sub-layer of first conductive material of said first conductive layer, the portion of said second conductive material adjacent said first conductive material being different from said sub-layer of said first conductive material; and
a second conductive layer having a top surface and a bottom surface, and being disposed over the second dielectric layer with its bottom surface adjacent to second dielectric layer, said second conductive layer having a portion therefor disposed over the conductive via.
6. The module of claim 5 wherein said first conductive layer comprises polysilicon and a top layer of aluminum.
7. The module of claim 5 wherein the doped region extends over substantially the entire top surface of the substrate.
8. The module of claim 5 wherein said substrate comprises a doping level of more than 1×10 −18 cm −3 and wherein the doped region is provided by the entire substrate.
9. The module of claim 5 wherein said first dielectric layer comprises silicon oxide.