Wafer-level testing apparatus and method
A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that electrically couples at least one die contact to an extended contact such as a bumped contact. The component further includes a bus conductor that traverses at least a portion of the die and electrically mates with corresponding bus conductors on other similarly prepared components on the wafer. Functional and nonfunctional dice are identified on the wafer and the nonfunctional dice are isolated from the wafer-level testing grid. Following test, dice may be subsequently tested or moved to singulation wherein the die-to-die interconnection is interrupted, allowing wafer-level tested components to be conventionally assembled. A wafer may be retrofit with the wafer-level redistribution circuit for facilitating wafer-level testing without requiring customization of test fixtures or software for avoiding testing of nonfunctional dice.
1. A method for testing a plurality of semiconductor components, comprising:
forming a plurality of dice on a semiconductor wafer, the plurality of dice each including at least one die contact; and
forming at least one wafer-level redistribution circuit on each of the plurality of dice for interconnection with others of the plurality of dice, the at least one wafer-level redistribution circuit including a redistribution circuit, and a bus conductor traversing each of the plurality of dice for electrically coupling with at least another one of the plurality of dice and at least one conductor for coupling the redistribution circuit to the bus conductor.
2. The method, as recited in claim 1 , further comprising forming an outer passivation layer on an exposed face of the semiconductor wafer covering the redistribution circuit and the bus conductor.
3. The method, as recited in claim 2 , further comprising probing each of the plurality of dice to determine functional and nonfunctional dice.
4. The method, as recited in claim 3 , further comprising storing location information on nonfunctional dice.
5. The method, as recited in claim 4 , further comprising isolating the at least one die contact on each of the nonfunctional dice.
6. The method, as recited in claim 5 , wherein isolating includes removing a portion of the outer passivation layer over at least one of the redistribution circuit and the bus conductor to form an open circuit between the at least one die contact and the bus conductor on nonfunctional dice.
7. The method, as recited in claim 5 , wherein isolating includes ablating of at least a portion of the at least one wafer-level redistribution circuit and the outer passivation layer.
8. The method, as recited in claim 5 , wherein isolating includes etching of at least a portion of the at least one wafer-level redistribution circuit and the outer passivation layer.
9. A method for manufacturing wafer-level testable dice, comprising:
forming a plurality of dice on a semiconductor wafer, the plurality of dice each including at least one die contact; and
forming at least one wafer-level redistribution circuit on each of the plurality of dice for interconnection with others of the plurality of dice, the at least one wafer-level redistribution circuit including a redistribution circuit, and a bus conductor traversing each of the plurality of dice for electrically coupling with at least another one of the plurality of dice and at least one other bus conductor for coupling the redistribution circuit to the bus conductor.
10. The method, as recited in claim 9 , further comprising isolating at least one of the at least one die contact on nonfunctional dice of the plurality of dice on the semiconductor wafer.
11. The method, as recited in claim 9 , further comprising probing each of the plurality of dice to determine functional and nonfunctional dice of the plurality of dice.
12. A method for fabricating a wafer-level testable semiconductor component, comprising:
forming a plurality of dice on a semiconductor wafer, the plurality of dice each including at least one die contact;
forming at least one wafer-level redistribution circuit on each of the plurality of dice for interconnection with others of the plurality of dice, the at least one wafer-level redistribution circuit including a redistribution circuit, and a bus conductor traversing each of the plurality of dice for electrically coupling with at least another one of the plurality of dice and at least one other bus conductor for coupling the redistribution circuit to the bus conductor;
isolating the at least one die contact on each nonfunctional die of the plurality of dice;
testing functional dice of the plurality of dice while integral with the semiconductor wafer; and
singulating one of the functional dice of the plurality of dice from the semiconductor component.
13. The method, as recited in claim 12 , wherein isolating further comprises probing each of the plurality of dice to determine the functional dice and the nonfunctional dice of the plurality of dice.
14. The method, as recited in claim 12 , further comprising burning-in the semiconductor component while the semiconductor component is integral with the semiconductor wafer.
15. A method for retrofitting an existing wafer layout for wafer-level testing, comprising:
on a semiconductor wafer including a plurality of dice with each die including at least one die contact, forming at least one wafer-level redistribution circuit on each of the plurality of dice for interconnection with others of the plurality of dice, the at least one wafer-level redistribution circuit including a redistribution circuit for coupling the at least one die contact to a respective bumped contact, a bus conductor traversing at least a portion of each of the plurality of dice for electrically coupling with at least another one of the plurality of dice, the at least one other bus conductor for coupling the redistribution circuit to the bus conductor; and
isolating at least one die contact on each nonfunctional die of the plurality of dice.
16. The method, as recited in claim 15 , wherein forming further comprises forming an outer passivation layer over the redistribution circuit and the bus conductor.
17. The method, as recited in claim 15 , wherein isolating further comprises probing each of the plurality of dice to determine functional dice and the nonfunctional dice of the plurality of dice.
18. The method, as recited in claim 16 , wherein isolating includes removing a portion of the outer passivation layer over the at least one wafer-level redistribution circuit and forming an open circuit between the at least one die contact and the bus conductor on the nonfunctional dice.
19. The method, as recited in claim 18 , wherein isolating includes ablating of at least a portion of the at least one wafer-level redistribution circuit and the outer passivation layer.
20. The method, as recited in claim 18 , wherein isolating includes etching of at least a portion of the at least one wafer-level redistribution circuit and the outer passivation layer.
21. A method for isolating nonfunctional dice from a wafer-level testing configuration, comprising:
forming at least one wafer-level redistribution circuit on each of a plurality of dice for interconnection with others of the plurality of dice, the at least one wafer-level redistribution circuit including a redistribution circuit for coupling at least one die contact to a respective bumped contact, a bus conductor traversing each of the plurality of dice for electrically coupling with at least another one of the plurality of dice and at least one other bus conductor for coupling the redistribution circuit to the bus conductor; and
isolating the at least one die contact on each nonfunctional die of the plurality of dice.
22. The method, as recited in claim 21 , further comprising forming an outer passivation layer over the at least one redistribution circuit and the at least one other bus conductor.
23. The method, as recited in claim 22 , wherein the outer passivation layer is selectively removable over at least a portion of one of the at least one redistribution circuit and the at least one other bus conductor for forming an electrical open circuit between the at least one die contact and the at least one other bus conductor when a die of the plurality of dice is determined to be defective.
24. The method, as recited in claim 23 , wherein isolating includes etching the at least one redistribution circuit to form the electrical open circuit.
25. The method, as recited in claim 23 , wherein isolating includes ablating the at least one redistribution circuit by a laser to form the electrical open circuit.