Semiconductor package free of substrate and fabrication method thereof
View Patent ↗A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.
1. A method for fabricating a semiconductor package, comprising the steps of:
preparing a metal carrier;
applying a dielectric material layer over a surface of the metal carrier, and forming a plurality of openings penetrating through tho dielectric material layer;
applying a solder material in each of the openings;
forming a first copper layer over the dielectric material layer and solder materials in the openings;
forming a second copper layer over the first copper layer, and patterning the first and second copper layers to form a plurality of conductive traces, each of the conductive traces having a terminal, wherein the first copper layer is smaller in thickness than the second copper layer;
mounting at least one chip on a predetermined portion of the conductive traces and electrically connecting the chip to the terminals;
forming an encapsulant to encapsulate the chip and conductive traces; and
removing the metal carrier to expose the dielectric material layer and solder materials.
2. The method of claim 1 , wherein the metal carrier is made of copper.
3. The method of claim 1 , wherein the solder material is tin/lead (Sn/Pb) alloy.
4. The method of claim 1 , wherein the first copper layer is formed by a process selected from the group consisting of electroless plating and sputtering.
5. The method of claim 1 , wherein the metal carrier is removed by an etching process.
6. The method of claim 1 , further comprising a step of:
implanting a plurality of solder balls on the exposed solder materials.
7. The method of claim 1 , further comprising a step of:
applying a metal layer on each of the terminals to allow the chip to be electrically connected to the terminals.
8. The method of claim 1 , further comprising a step of:
applying an insulating layer over the conductive traces, with the terminals of the conductive traces being exposed to outside of the insulating layer.
9. The method of claim 7 , wherein the metal layer is made of a material selected from the group consisting of silver (Ag) and nickel/gold (Ni/Au) alloy.
10. The method of claim 7 , wherein the solder material, second copper layer and metal layer are formed by an electrical plating process.
11. The method of claim 7 , wherein the chip is electrically connected to the terminals by a plurality of conductive elements selected from the group consisting of bonding wires and solder bumps.
12. The method of claim 8 , wherein the insulating layer is made of a material selected from the group consisting of solder mask and polyimide.