IP Library Granted Patent US 6,884,658
Granted Patent B2
US 6,884,658 · App. 09/992,580 · Granted Apr 26, 2005

Die stacking scheme

Assignee: Micron Technology, Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,884,658
App. No.
09/992,580
Granted
Apr 26, 2005
Kind
B2
Abstract

An improved die stacking scheme is provided. In accordance with one embodiment of the present invention, a multiple die semiconductor assembly is provided comprising a substrate, first and second semiconductor dies, and at least one decoupling capacitor. The first semiconductor die defines a first active surface. The first active surface includes at least one conductive bond pad. The second semiconductor die defines a second active surface, the second active surface includes at least one conductive bond pad. The first semiconductor die is interposed between the substrate and the second semiconductor die such that a surface of the second semiconductor die defines an uppermost die surface of the multiple die semiconductor assembly and such that a surface of the first semiconductor die defines a lowermost die surface of the multiple die semiconductor assembly. The decoupling capacitor is secured to the uppermost die surface and is conductively coupled to at least one of the first and second semiconductor dies.

Claims (34)

1. A method of assembling a printed circuit board, said method comprising:

providing a substrate including a first surface and conductive contacts included on said first surface;

providing a first semiconductor die including a pair of major surfaces, wherein

one of said pair of major surfaces of said first die defines a first active surface,

the other of said major surfaces of said first die defines a first stacking surface, and

said first active surface includes a plurality of conductive bond pads;

electrically coupling said first active surface to said substrate with a plurality of topographic contacts extending from respective conductive bond pads on said first active surface to corresponding conductive contacts on said first surface of said substrate;

providing a second semiconductor die including a pair of major surfaces, wherein

one of said pair of major surfaces of said second die defines a second active surface,

the other of said major surfaces of said second die defines a second stacking surface,

said second active surface includes a plurality of conductive bond pads, and

said first stacking surface is devoid of conductive bond pads;

securing said first stacking surface to said second stacking surface;

securing a single decoupling capacitor to said second active surface;

providing a pair of conductive lines, each of said conductive lines connecting a terminal of said decoupling capacitor, a bond pad on said second active surface, and a conductive contact on said first surface of said substrate;

electrically coupling said conductive contact on said first surface of said substrate to said first semiconductor die via one of said plurality of topographic contacts extending from respective conductive bond pads on said first active surface to corresponding conductive contacts on said first surface of said substrate;

arranging said pair of conductive lines such that said decoupling capacitor is connected across V ss and V cc pins of said first and second semiconductor dies;

positioning a printed circuit board such that a first surface of said printed circuit board faces said substrate; and

providing a plurality of topographic contacts extending from said substrate to said first surface of said printed circuit board.

2. A method of stacking a plurality of semiconductor die, said method comprising:

providing a substrate including a first surface and conductive contacts included on said first surface;

providing a first semiconductor die including a pair of major surfaces, wherein

one of said pair of major surfaces of said first die defines a first active surface,

the other of said major surfaces of said first die defines a first stacking surface, and

said first active surface includes at least one conductive bond pad;

electrically coupling said first active surface to said substrate by at least one topographic contact extending from a conductive bond pad on said first active surface to a conductive contact on said first surface of said substrate;

providing a second semiconductor die including a pair of major surfaces, wherein

one of said pair of major surfaces of said second die defines a second active surface,

the other of said major surfaces of said second die defines a second stacking surface, and

said second active surface includes at least one conductive bond pad;

securing said first stacking surface to said second stacking surface;

securing at least one decoupling capacitor to said second active surface; and

providing at least one conductive line connecting said decoupling capacitor, a bond pad on said second active surface, and a conductive contact on said first surface of said substrate.

3. The method as claimed in claim 2 further comprising providing at least one conductive line extending from a bond pad on said second active surface to a conductive contact on said first surface of said substrate.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Division 0980442100 · Mar 30, 2001
Related Publication 20020137258A1 · Sep 26, 2002