Transistor-type ferroelectric nonvolatile memory element
View Patent ↗A transistor-type ferroelectric nonvolatile memory element having an MFMIS (metal-ferroelectric-metal-insulator-semiconductor) structure that can be highly densely integrated. The MFMIS transistor has a constitution in which the MFM (metal-ferroelectric-metal) structure and the MIS (metal-insulator-semiconductor) structure are stacked up and down on nearly the same area, and the lower MIS structure has means for increasing the effective area of the MIS capacitance. Means for increasing the effective area of the capacitor is a trench in the semiconductor substrate, ruggedness in the MIS structure or a MIN (metal-insulator-metal) structure.
1. A transistor-type ferroelectric nonvolatile memory element having an MFMIS (metal-ferroelectric-metal-insulator-semiconductor) structure formed in a semiconductor substrate, comprising:
an MFM (metal-ferroelectric-metal) structure and an MIS (metal-insulator-semiconductor) structure vertically arranged with the MFM structure above a level of the MIS structure; and
means for increasing an effective area of a capacitance of the MIS structure as compared with the effective area of a capacitance of the MFM structure, the means for increasing the effective area including a substrate layer of the MIS structure being formed as one of a trench and a rugged portion such as to increase a surface area of an interface of an insulator layer and the substrate layer of the MIS structure.
2. A transistor-type ferroelectric nonvolatile memory element according to claim 1 , wherein the trench is formed in the semiconductor substrate, the MIS structure is formed in the trench, the MFM structure is laminated on the trench nearly in parallel with a main surface of the semiconductor substrate, and means for increasing the effective area is the trench.
3. A transistor-type ferroelectric nonvolatile memory element according to claim 2 , wherein the MIS structure is an MIS transistor of the nonvolatile memory element, regions of source, base and drain of the MIS transistor are formed in the semiconductor substrate in order of source, base and drain from a lower side of the semiconductor substrate, and the means for increasing the effective area is a gate structure of the MIS transistor formed in the semiconductor substrate on an inner surface of the trench.
4. A transistor-type ferroelectric nonvolatile memory element according to claim 2 , wherein the MIS structure is an MIS transistor of the nonvolatile memory element, regions of source, base and drain of the MIS transistor are formed in the semiconductor substrate in order of drain, base and source from a lower side of the semiconductor substrate, and the means for increasing the effective area is a gate structure of the MIS transistor formed in the semiconductor substrate on an inner surface of the trench.
5. A transistor-type ferroelectric nonvolatile memory element according to claim 2 , wherein the MIS structure is a MIS transistor of the nonvolatile memory element, and regions of source and drain of the MIS transistor are separated by the trench.
6. A transistor-type ferroelectric nonvolatile memory element according to claim 1 , wherein the MIS structure includes the rugged portion therein, the means for increasing the effective area is constituted by the rugged portion, the upper part of the MIS structure is flat, and the MFM structure is laminated thereon.
7. A transistor-type ferroelectric nonvolatile memory element according to claim 1 , wherein the means for increasing the effective area is constituted by an MIM (metal-insulator-metal) structure provided between the MFM structure and the MIS structure.
8. A transistor-type ferroelectric nonvolatile memory element according to claim 1 , wherein the effective area of a metal layer on the ferroelectric layer of the MFM structure is smaller than that of the ferroelectric layer.