Method for software pipelining of irregular conditional control loops
A method for software pipelining of irregular conditional control loops including pre-processing the loops so they can be safely software pipelined. The pre-processing step ensures that each original instruction in the loop body can be over-executed as many times as necessary. During the pre-processing stage, each instruction in the loop body is processing in turn (N 4 ). If the instruction can be safely speculatively executed, it is left alone (N 6 ). If it could be safely speculatively executed except that it modifies registers that are live out of the loop, then the instruction can be pre-processed using predication or register copying (N 7 , N 8 , N 9 ). Otherwise, predication must be applied (N 10 ). Predication is the process of guarding an instruction. When the guard condition is true, the instruction executes as though it were unguarded. When the guard condition is false, the instruction is nullified.
1. A method of pipelining program loops having irregular loop control comprises the steps of:
determining which instructions in loop code in a memory may be speculatively executed, if it is determined that the instruction would be able to be speculatively executed except that it modifies a register that is alive out of the loop performing the steps of:
storing in a computer memory a set of registers that are modified by said instruction and are alive out of the loop, and
modifying the program code so that the values of those registers are saved to a temporary register during all proper iterations, and
copying back to said registers the values of the temporary register once the loop is completed.
2. The method of claim 1 , applied to any program loops wherein a minimum trip count is reduced to one.
3. The method of claim 1 , applied to any program loops wherein a need for a multiversion code is eliminated.
4. A method for software pipelining of irregular conditional control loops includes pre-processing the loops so they can be safely software pipelined, comprising the steps of:
pre-processing each instruction in the loop in turn;
if the instruction can be safely speculatively executed, leaving the instruction alone;
if it could be safely speculatively executed except that it modifies registers that are live out of the loop, pre-processing the instruction using register copying and otherwise using predication.