Active load device that enables biasing of a very wide band distributed amplifier circuit with gain control
The invention relates to a very wide band amplifier circuit including a distributed amplification cell ( 100 ) connected to a biasing cell ( 200 ), the amplification cell ( 100 ) including several transistors (T 1 ) connected in parallel between a drain line and a grid line, each terminated at one of its ends by a load (Zin, Zout), the biasing cell ( 200 ) including at least one transistor (T 2 ) connected between a power source (V DD ) and the drain line of the amplification cell ( 100 ), said biasing cell having an overall impedance equal to the impedance of the load (Zout) connected to the end of the drain line of the amplification cell ( 100 ), characterized in that the grid (G 2 ) of the transistor (T 2 ) of the biasing cell ( 200 ) is connected to the node ( 201 ) of a divider bridge (R 1 R 2 , R 1 T 3 ) so as to set its grid (G 2 ) potential (V G2 ), and in that the grid (G 2 ) and the source (S 2 ) of said transistor (T 2 ) are connected together by means of at least one capacitor (C 1 , C 2 ).
1. Very wide band amplifier circuit including a distributed amplification cell ( 100 ) connected to a biasing cell ( 200 ), the amplification cell ( 100 ) including several transistors (T 1 ) connected in parallel between as drain line and a grid line, each terminated at one of its ends by a load (Zin, Zout), the biasing cell ( 200 ) including at least one transistor (T 2 ) connected between a power source (V DD ) and the drain line of the amplification cell ( 100 ), said biasing cell having an overall impedance equal to the impedance of the load (Zout) connected to the end of the drain line of the amplification cell ( 100 ), characterized in that the grid (G 2 ) of the transistor (T 2 ) of the biasing cell ( 200 ) is connected to the node ( 201 ) of the divider bridge (R 1 R 2 , R 1 T 3 ) so as to set its grid (G 2 ) potential V G2 ), and in that the grid (G 2 ) and the source (S 2 ) of said transistor (T 2 ) are connected together by means of at least one capacitor (C 1 , C 2 ).
2. Amplifier circuit as claimed in claim 1 , characterized in that it includes a resistor (R) mounted in series with the capacitor (C) between the grid (G 2 ) and the source (S 2 ) of the transistor (T 2 ) of the biasing cell ( 200 ).
3. Amplifier circuit as claimed in claim 1 or claim 2 , characterized in that it includes a resistor (R 3 ) connected between the grid (G 2 ) of the transistor (T 2 ) and the node ( 201 ) of the divider bridge (R 1 R 2 , R 1 T 3 ).
4. Amplifier circuit as claimed in claim 1 or claim 2 , characterized in that the divider bridge (R 1 T 3 ) includes at least one transistor (T 3 ).
5. Amplifier circuit as claimed in claim 1 or claim 2 , characterized in that the biasing cell ( 200 ) includes several transistors (T 2 ) arranged in parallel and several divider bridges (R 1 R 2 ) arranged in parallel and in that each of the transistors (T 2 ) is connected by its grid (G 2 ) to one of the divider bridges (R 1 R 2 ).
6. Amplifier circuit as claimed in claim 1 or claim 2 , characterized in that it includes at least one resistor (R 5 ) mounted in parallel with the biasing cell ( 200 ).
7. Amplifier circuit as claimed in claim 1 or claim 2 , characterized in that it includes at least one resistor (R 6 ) mounted in series with the biasing cell ( 200 ).
8. Amplifier circuit as claimed in claim 1 or claim 2 , characterized in that it includes an inductor (L 7 ) and a resistor (R 7 ) arranged in parallel, mounted in series with the biasing cell ( 200 ).
9. Amplifier circuit as claimed in claim 1 or claim 2 , characterized in that it includes at least one resistor (R 8 ) and one capacitor (C 8 ) arranged in series, connected between the drain (D 2 ) of the transistor (T 2 ) and the ground.
10. Biasing cell ( 200 ) for amplifier circuit, characterized in that it includes at least one transistor (T 2 ) designed to be connected between a power supply (V DD ) and a drain line of an amplification, cell ( 100 ), characterized in that the grid (G 2 ) of the transistor (T 2 ) of the biasing cell ( 200 ) is connected to the node ( 201 ) of a divider bridge (R 1 R 2 , R 1 T 3 ) so as to set its grid (G 2 ) potential (V G2 ), and in that the grid (G 2 ) and the source (S 2 ) of said transistor (T 2 ) are connected together by means of at least one capacitor (C 1 , C 2 ).