Semiconductor device
A pin diode is formed by a p + collector region, an n type buffer region, an n − region and an n + cathode region. A trench is formed from the surface of n + cathode region through n + cathode region to reach n − region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n + cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n + cathode region. An anode electrode is formed to be electrically connected to p + collector region. The n + cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.
1. A semiconductor device in which current flows between first and second main surfaces of an intrinsic or a first conductivity type semiconductor substrate, comprising:
a first impurity region of a second conductivity type formed on said first main surface side of said semiconductor substrate; and
a second impurity region of the second conductivity type formed on said second main surface of said semiconductor substrate, sandwiching, with said first impurity region, a low concentration region of said semiconductor substrate; wherein
said semiconductor substrate includes a trench reaching said low concentration region of said semiconductor substrate from said first main surface through said first impurity region;
said device further comprising:
a third impurity region of the first conductivity type on said first impurity region to be in contact with a sidewall of said trench at said first main surface of said semiconductor substrate;
a fourth impurity region of the second conductivity type having a higher concentration than said first impurity region, formed on said first impurity region and adjacent to said third impurity region at said first main surface of said semiconductor substrate;
a control electrode layer formed in said trench to oppose to said first and third impurity regions and said low concentration region of said semiconductor substrate with an insulating film interposed, for controlling current flowing between said first and second main surfaces by an applied control voltage;
a first electrode layer formed on said first main surface of said semiconductor substrate and electrically connected to said third and fourth impurity regions; and
a second electrode layer formed on said second main surface of said semiconductor substrate and electrically connected to said second impurity region; wherein
the following expression is satisfied where Dt represents depth of said trench from said first main surface, Wt represents width of said trench, De represents depth of said third impurity region from said first main surface, We represents width of said third impurity region from one of said trenches to another of said trenches, and Pt represents pitch of adjacent said trenches:
2
(
We
+
Dt
-
De
)
+
Wt
2
(
We
+
Dt
-
De
)
+
Pt
≧
0.4
.