IP Library › Granted Patent US 6,900,503
Granted Patent B2
US 6,900,503 · App. 10/649,222 · Granted May 31, 2005

SRAM formed on SOI substrate

Assignee: Samsung Electronics, Co., Ltd.
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Quick Facts
Patent No.
US 6,900,503
App. No.
10/649,222
Granted
May 31, 2005
Kind
B2
Abstract

An SRAM capable of reducing the overall area consumed by the circuit and capable of improving the mobility and operational characteristics of a PMOS transistor is provided. The SRAM is formed on an SOI substrate having first and second active areas. A first access NMOS transistor and a first inverter, which is constituted by a first drive NMOS transistor and a first load PMOS transistor, are formed on the first active area of the SOI substrate. A second access NMOS transistor and a second inverter, which is constituted by a first drive NMOS transistor and a first load PMOS transistor, are formed on the second active area of the SOI substrate. Here, the channels of the first and second load PMOS transistors extend so that carriers move in a [110] silicon crystallization growth direction. In each active area, the drain (or source) of an access NMOS transistor, the drain of a drive NMOS transistor, and the drain of a load PMOS transistor contact one another in a shared region. Because the SRAM is formed on the SOI substrate, the size of the resulting chip can be reduced. Also, because the channels of the first and second load PMOS transistors extend so that carriers move in the [110] silicon crystallization growth direction, the mobility of the PMOS transistors is improved.

Claims (60)

1. An SRAM comprising:

first and second access NMOS transistors;

a first drive NMOS transistor and a first load PMOS transistor which constitute a first inverter which is selectively activated in response to the operation of the second access NMOS transistor; and

a second drive NMOS transistor and a second load PMOS transistor which constitute a second inverter which is selectively activated in response to the operation of the first access NMOS transistor,

wherein the transistors are formed on active areas of an SOI substrate, and wherein a portion of an active area where a load PMOS transistor is formed extends so as to make a predetermined acute angle with a portion of an active area where a drive NMOS transistor is formed.

2. The SRAM of claim 1 , wherein the predetermined angle is between 30° and 60°.

3. The SRAM of claim 1 , wherein the predetermined angle is 45°.

4. The SRAM of claim 1 , wherein the portion of the active area where a load PMOS transistor is formed extends in a [110] silicon crystallization growth direction.

5. The SRAM of claim 1 , wherein the active area comprises:

a first active area where the first access NMOS transistor and the first inverter are formed; and

a second active area where the second access NMOS transistor and the second inverter are formed.

6. The SRAM of claim 5 , wherein the drain region of the first drive NMOS transistor and the drain region of the first load PMOS transistor contact each other on the first active area of a silicon layer of the SOI substrate, and wherein the drain region of the second drive NMOS transistor and the drain region of the second load PMOS transistor contact each other on the second active area of the silicon layer of the SOI substrate.

7. The SRAM of claim 6 , wherein one of the drain and source of the first access NMOS transistor, the drain of the first drive NMOS transistor, and the drain of the first load PMOS transistor are formed in a shared region of the first active area so as to be electrically connected to one another, and wherein one of the dram and source of the second access NMOS transistor, the drain of the second drive NMOS transistor, and the drain of the second load PMOS transistor are formed in a shared region of the second active area so as to be electrically connected to one another.

8. The SRAM of claim 1 , wherein one of the drain and source of the first access NMOS transistor, the drain of the first drive NMOS transistor, and the drain of the first load PMOS transistor are formed in a shared region of the first active area so as to be electrically connected to one another, and wherein one of the drain and source of the second access NMOS transistor, the drain of the second drive NMOS transistor, and the drain of the second load PMOS transistor are formed in a shared region of the second active area so as to be electrically connected to one another.

9. An SRAM comprising:

a semiconductor substrate;

a first active area formed on the semiconductor substrate and having a first access NMOS transistor and a first inverter which is comprised of a first drive NMOS transistor and a first load PMOS transistor; and

a second active area formed on the semiconductor substrate and having a second access NMOS transistor and a second inverter which is comprised of a second drive NMOS transistor and a second load PMOS transistor,

wherein a portion of each of the first and second active areas where the first and second load PMOS transistors are formed, respectively, extends so as to make a predetermined acute angle with a portion of each of the first and second active areas where the NMOS transistors are formed.

10. The SRAM of claim 9 , wherein the predetermined angle is between 30° and 60°.

11. The SRAM of claim 9 , wherein the predetermined angle is 45°.

12. The SRAM of claim 9 , wherein the portion of the active area where a load PMOS transistor is formed extends in the [110] silicon crystallization growth direction.

13. The SRAM of claim 9 , wherein the drain region of the first drive NMOS transistor and the drain region of the first load PMOS transistor contact each other on the first active area of the semiconductor substrate, and wherein the drain region of the second drive NMOS transistor and the drain region of the second load PMOS transistor contact each other on the second active area of the semiconductor substrate.

14. The SRAM of claim 13 , wherein one of the drain and source of the first access NMOS transistor, the drain of the first drive NMOS transistor, and the drain of the first load PMOS transistor are formed in a shared region of the first active area so as to be electrically connected to one another, and wherein one of the drain and source of the second access NMOS transistor, the drain of the second drive NMOS transistor, and the drain of the second load PMOS transistor are formed in a shared region of the second active area so as to be electrically connected to one another.

15. The SRAM of claim 9 , wherein one of the drain and source of the first access NMOS transistor, the drain of the first drive NMOS transistor, and the drain of the first load PMOS transistor are formed in a shared region of the first active area so as to be electrically connected to one another, and wherein one of the drain and source of the second access NMOS transistor, the drain of the second drive NMOS transistor, and the drain of the second load PMOS transistor are formed in a shared region of the second active area so as to be electrically connected to one another.

16. The SRAM of claim 14 , wherein the semiconductor substrate is an SOI substrate.

17. An SRAM formed with first and second access NMOS transistors, a first drive NMOS transistor and a first load PMOS transistor which constitute a first inverter that is selectively activated in response to the operation of the second access NMOS transistor, and a second drive NMOS transistor and a second load PMOS transistor which constitute a second inverter that is selectively activated in response to the operation of the first access NMOS transistor, the SRAM comprising:

an SOI substrate;

a first active area formed on the SOI substrate and having a first access NMOS transistor and a first inverter which is comprised of a first drive NMOS transistor and a first load PMOS transistor; and

a second active area formed on the SOI substrate and having a second access NMOS transistor and a second inverter which is comprised of a second drive NMOS transistor and a second load PMOS transistor,

wherein a portion of each of the first and second active areas where the first and second load PMOS transistors are formed, respectively, extends so as to make a predetermined acute formed.

18. The SRAM of claim 17 , wherein the predetermined angle is between 30° and 60°.

19. The SRAM of claim 17 , wherein the predetermined angle is 45°.

20. The SRAM of claim 17 , wherein the portion of the active area where a load PMOS transistor is formed extends in the [110] silicon crystallization growth direction.

21. An SRAM formed with first and second access NMOS transistors, a first drive NMOS transistor and a first load PMOS transistor which constitute a first inverter that is selectively activated in response to the operation of the second access NMOS transistor, and a second drive NMOS transistor and a second load PMOS transistor which constitute a second inverter that is selectively activated in response to the operation of the first access NMOS transistor, the SRAM comprising:

an SOI substrate;

a first active area formed on the SOI substrate and having a first access NMOS transistor and a first inverter which is comprised of a first drive NMOS transistor and a first load PMOS transistor; and

a second active area formed on the SOI substrate and having a second access NMOS transistor and a second inverter which is comprised of a second drive NMOS transistor and a second load PMOS transistor,

wherein a portion of each of the first and second active areas where the first and second load PMOS transistors are formed, respectively, extends so as to make a predetermined acute angle with a portion of each of the first and second active areas where the NMOS transistors are formed,

wherein one of the drain and source of the first access NMOS transistor, the drain of the first drive NMOS transistor, and the drain of the first load PMOS transistor are formed in a shared region of the first active area so as to be electrically connected to one another, and

wherein one of the drain and source of the second access NMOS transistor, the drain of the second drive NMOS transistor, and the drain of the second load PMOS transistor are formed in a shared region of the second active area so as to be electrically connected to one another.

22. The SRAM of claim 21 , wherein the predetermined angle is between 30° and 60°.

23. An SRAM formed with first and second access NMOS transistors, a first drive NMOS transistor and a first load PMOS transistor which constitute a first inverter that is selectively activated in response to the operation of the second access NMOS transistor, and a second drive NMOS transistor and a second load PMOS transistor which constitute a second inverter that is selectively activated in response to the operation of the first access NMOS transistor, the SRAM comprising:

an SOI substrate;

a first active area formed on the SOI substrate and having a first access NMOS transistor and a first inverter which is comprised of a first drive NMOS transistor and a first load PMOS transistor; and

a second active area formed on the SOI substrate and having a second access NMOS transistor and a second inverter which is comprised of a second drive NMOS transistor and a second load PMOS transistor,

wherein a portion of each of the first and second active areas where the first and second load PMOS transistors are formed extends so as to make an angle of approximately 45 degrees with a portion of each of the first and second active areas where the NMOS transistors are formed,

wherein one of the drain and source of the first access NMOS transistor, the drain of the first drive NMOS transistor, and the drain of the first load PMOS transistor are formed in a shared region of the first active area so as to be electrically connected to one another, and wherein one of the drain and source of the second access NMOS transistor, the drain of the second drive NMOS transistor, and the drain of the second load PMOS transistor are formed in a shared region of the second active area so as to be electrically connected to one another.

24. An SRAM comprising:

first and second access NMOS transistors;

a first drive NMOS transistor and a first load PMOS transistor which constitute a first inverter which is selectively activated in response to the operation of the second access NMOS transistor; and

a second drive NMOS transistor and a second load PMOS transistor which constitute a second inverter which is selectively activated in response to the operation of the first access NMOS transistor,

wherein the transistors are formed on active areas of an SOI substrate, and wherein a portion of an active area where a load PMOS transistor is formed extends so as to make a predetermined angle with a portion of an active area where a drive NMOS transistor is formed;

wherein the portion of the active area where a load PMOS transistor is formed extends in a silicon crystallization growth direction.

25. An SRAM comprising:

a semiconductor substrate;

a first active area formed on the semiconductor substrate and having a first access NMOS transistor and a first inverter which is comprised of a first drive NMOS transistor and a first load PMOS transistor; and

a second active area formed on the semiconductor substrate and having a second access NMOS transistor and a second inverter which is comprised of a second drive NMOS transistor and a second load PMOS transistor,

wherein a portion of each of the first and second active areas where the first and second load PMOS transistors are formed, respectively, extends so as to make a predetermined angle with a portion of each of the first and second active areas where the NMOS transistors are formed;

wherein the portion of the active area where a load PMOS transistor is formed extends in the [110] silicon crystallization growth direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2003
From: OH, CHANG-BONG; KIM, YONG-WUG
To: SAMSUNG ELECTRONICS, CO., LTD.
Reel/Frame 014441/0089 →
Priority Claims (1)
KR 10-2002-0053329 · Sep 4, 2002 · national
Continuity (1)
Related Publication 20040051143A1 · Mar 18, 2004