IP Library › Granted Patent US 6,908,799
Granted Patent B2
US 6,908,799 · App. 10/673,319 · Granted Jun 21, 2005

High electron mobility transistor and method of manufacturing the same

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 6,908,799
App. No.
10/673,319
Granted
Jun 21, 2005
Kind
B2
Abstract

A high electron mobility transistor comprises a GaN-based electron accumulation layer formed on a substrate, an electron supply layer formed on the electron accumulation layer, a source electrode and a drain electrode formed on the electron supply layer and spaced from each other, a gate electrode formed on the electron supply layer between the source and drain electrodes, and a hole absorption electrode formed on the electron accumulation layer so as to be substantially spaced from the electron supply layer. Since the hole absorption electrode is formed on the electron absorption layer in order to prevent holes generated by impact ionization from being accumulated on the electron accumulation layer, a kink phenomenon is prevented. Good drain-current/voltage characteristics are therefore obtained. A high power/high electron mobility transistor is provided with a high power-added efficiency and good linearity.

Claims (17)

1. A method for manufacturing a high electron mobility transistor, comprising:

forming an electron accumulation layer on a substrate;

forming an isolated element region on the electron accumulation layer, the isolated element region having an electron supply layer;

forming a source electrode and a drain electrode on the electron supply layer of the isolated element region, being spaced for each other; and

forming a hole absorption electrode on the electron accumulation layer, the hole absorption electrode being spaced from the electron supply layer and simultaneously forming a gate electrode on the electron supply layer of the isolated element region.

2. The method of claim 1 , wherein

the forming of the isolated element region includes selectively removing the electron supply layer to isolate the element region.

3. The method of claim 2 , wherein

the forming of the hole absorption electrode includes selectively removing the electron supply layer.

4. The method of claim 3 , wherein

the forming of the hole absorption electrode includes forming the hole absorption electrode on the electron accumulation layer via a semiconductor layer having a smaller bandgap width than that of the electron accumulation layer.

5. The method of claim 3 , wherein

the forming of the hole absorption electrode includes forming the hole absorption electrode on the electron accumulation layer via a p-type semiconductor layer.

6. The method of claim 3 , wherein

the forming of the hole absorption electrode includes forming the hole absorption electrode adjacent to the source electrode.

7. The method of claim 3 , wherein

the forming of the hole absorption electrode includes forming the hole absorption electrode in parallel with the gate electrode in a gate width direction having the substantially the same length as that of the source electrode in the gate width direction.

Priority Claims (1)
JP 2000-094574 · Mar 30, 2000 · national
Continuity (3)
Continuation 1037508400 · Feb 28, 2003
Division 0977882300 · Feb 8, 2001
Related Publication 20040061130A1 · Apr 1, 2004