Optoelectronic devices having arrays of quantum-dot compound semiconductor superlattices therein
Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm. The semiconductor nano-pillars are also preferably homoepitaxial or heteroepitaxial with the semiconductor layer.
1. An opto-electronic device, comprising:
a substrate comprising a first III-V semiconductor layer;
an electrically insulating layer that extends on the first III-V semiconductor layer and comprises an array of non-photolithographically defined nanopores therein;
an array of vertical quantum-dot superlattices in the array of nanopores; and
a second III-V semiconductor layer on said array of vertical quantum-dot superlattices.
2. The device of claim 1 , wherein the nanopores in the array have an average diameter in a range between about 8 nm and about 50 nm.
3. The device of claim 1 , wherein the first III-V semiconductor layer is an N-type semiconductor layer; and wherein the second III-V semiconductor layer is a P-type semiconductor layer.
4. The device of claim 1 , wherein the first III-V semiconductor layer is an N-type Al x Ga 1-x As layer; and wherein the second III-V semiconductor layer is a P-type Al x Ga 1-x As layer.
5. The device of claim 1 , wherein the first III-V semiconductor layer comprises an N-type GaAs layer and an N-type Al x Ga 1-x As layer on the N-type GaAs layer.
6. The device of claim 5 , wherein said electrically insulating layer comprises an anodized aluminum oxide layer having the array of non-photolithographically defined nanopores therein.
7. The device of claim 6 , wherein each of a plurality of vertical quantum-dot superlattices in the array of nanopores comprises an alternating arrangement of InGaAs and GaAs dots therein.
8. The device of claim 7 , wherein said second III-V semiconductor layer comprises a P-type Al x Ga 1-x As layer that contacts said electrically insulating layer and a P-type GaAs layer that extends on the P-type Al x Ga 1-x As layer.
9. The device of claim 5 , wherein said electrically insulating layer comprises a silicon dioxide layer having the array of non-photolithographically defined nanopores therein.
10. The device of claim 9 , wherein each of a plurality of vertical quantum-dot superlattices in the array of nanopores comprises an alternating arrangement of InGaAs and GaAs dots therein.
11. The device of claim 10 , wherein said second III-V semiconductor layer comprises a P-type Al x Ga 1-x As layer that contacts said electrically insulating layer and a P-type GaAs layer that extends on the P-type Al x Ga 1-x As layer.