Active matrix display device
View Patent ↗In an active matrix display device, a circuit including at least five thin film transistors (TFTs) which are provided with an approximately M-shaped semiconductor region for a single pixel electrode and gate lines and a capacitances line which cross the M-shaped semiconductor region, is used as a switching element. Each of the TFT have offset regions and lightly doped drain (LDD) regions. Then, by supplying a selection signal to the gate lines, the TFTs are operated, thereby writing data to the pixel, while a suitable voltage is supplied to the capacitance line, a channel is formed thereunder and it becomes a capacitor. Thus the amount of discharge from the pixel electrode is reduced by the capacitor.
1. A display device comprising:
a gate line over a substrate;
an image signal line extending across the gate line over the substrate;
a pixel electrode disposed at an intersection of the gate line and the image signal line;
at least first, second, and third thin film transistors disposed between the image signal line and the pixel electrode,
wherein each gate electrode of the first, second, and third thin film transistors is commonly connected to the gate line,
wherein an impurity region of the first thin film transistor is connected to the image signal line, and an impurity region of the third thin film transistor is electrically connected to the pixel electrode, and
wherein the second and third thin film transistors are connected in series.
2. A device according to claim 1 , wherein each of the first, second, and third thin film transistors comprise one approximately M-shaped semiconductor film.
3. A display device comprising:
a gate line over a substrate;
an image signal line extending across the gate line over the substrate;
a pixel electrode disposed at an intersection of the gate line and the image signal line;
at least first, second, third, and fourth thin film transistors disposed between the image signal line and the pixel electrode,
wherein an impurity region of the first thin film transistor is connected to the image signal line, and a gate electrode of the fourth thin film transistor is connected to a capacitance line,
wherein the second and third thin film transistors are connected in series, and
wherein a storage capacitor is provided between the pixel electrode and the capacitance line.
4. A device according to claim 3 , wherein each of the first, second, third, and fourth thin film transistors comprise one approximately M-shaped semiconductor film.
5. A display device comprising:
a gate line over a substrate;
an image signal line extending across the gate line over the substrate;
a pixel electrode disposed at an intersection of the gate line and the image signal line;
at least first, second, and third thin film transistors disposed between the image signal line and the pixel electrode,
wherein an impurity region of the first thin film transistor is connected to the image signal line, and an impurity region of the third thin film transistor is electrically connected to the pixel electrode,
wherein a gate electrode of the second thin film transistor is connected to a capacitance line, and
wherein a storage capacitor is provided between the pixel electrode and the capacitance line.
6. A device according to claim 5 , wherein each of the first, second, and third thin film transistors comprise one approximately M-shaped semiconductor film.
7. A display device comprising:
a gate line over a substrate;
an image signal line extending across the gate line over the substrate;
a capacitance line extending parallel to the gate line over the substrate;
a pixel electrode disposed at an intersection of the gate line and the image signal line;
at least first, second, third, and fourth thin film transistors disposed between the image signal line and the pixel electrode,
wherein an impurity region of the first thin film transistor is connected to the image signal line, and an impurity region of the third thin film transistor is electrically connected to the pixel electrode,
wherein gate electrodes of the second and fourth thin film transistors are connected to the capacitance line.
8. A device according to claim 7 , wherein each of the first, second, third, fourth thin film transistors comprise one approximately M-shaped semiconductor film.
9. A display device comprising:
a gate line over a substrate;
an image signal line extending across the gate line over the substrate;
a pixel electrode disposed at an intersection of the gate line and the image signal line; and
at least first, second, and third thin film transistors disposed in series between the image signal line and the pixel electrode,
wherein an impurity region of the first thin film transistor is connected to the image signal line, and an impurity region of the third thin film transistor is electrically connected to the pixel electrode, and
wherein each gate electrode of the first, second, and third thin film transistors is commonly connected to the gate line.
10. A display device comprising:
a gate line over a substrate;
an image signal line extending across the gate line over the substrate;
a pixel electrode disposed at an intersection of the gate line and the image signal line; and
at least first, second, and third thin film transistors disposed in series between the image signal line and the pixel electrode,
wherein an impurity region of the first thin film transistor is connected to the image signal line, and an impurity region of the third thin film transistor is electrically connected to the pixel electrode,
wherein each gate electrode of the first, second, and third thin film transistors is commonly connected to the gate line, and
wherein each channel region of the first, second, and third thin film transistors is included in a same semiconductor layer.
11. A display device comprising:
a gate line over a substrate;
an image signal line extending across the gate line over the substrate;
a pixel electrode disposed at an intersection of the gate line and the image signal line;
at least first, second, and third thin film transistors disposed in series between the image signal line and the pixel electrode; and
a storage capacitor electrically connected to the pixel electrode,
wherein an impurity region of the first thin film transistor is connected to the image signal line, and an impurity region of the third thin film transistor is electrically connected to the pixel electrode, and
wherein each gate electrode of the first, second, and third thin film transistors is commonly connected to the gate line.
12. A display device according to claim 11 , wherein the storage capacitor comprises the pixel electrode and a capacitance line.
13. A display device comprising:
a gate line over a substrate;
an image signal line extending across the gate line over the substrate;
a pixel electrode disposed at an intersection of the gate line and the image signal line;
at least first, second, and third thin film transistors disposed in series between the image signal line and the pixel electrode; and
a storage capacitor electrically connected to the pixel electrode,
wherein an impurity region of the first thin film transistor is connected to the image signal line, and an impurity region of the third thin film transistor is electrically connected to the pixel electrode,
wherein each gate electrode of the first, second, and third thin film transistors is commonly connected to the gate line, and
wherein each channel region of the first, second, and third thin film transistors is included in a same semiconductor layer.
14. A display device according to claim 13 , wherein the storage capacitor comprises the pixel electrode and a capacitance line.