Approach to prevent undercut of oxide layer below gate spacer through nitridation
View Patent ↗A method is provided for the removal of liner oxide from the surface of a gate electrode during the creation of the gate electrode. A layer of gate oxide is formed over the surface of a substrate, a layer of gate electrode is deposited over the layer of gate oxide. The gate electrode is deposited, gate spacers are formed over the liner oxide, exposing surfaces of the liner oxide. The created structure is nitrided by a plasma stream containing N 2 /H 2 , reducing the etch rate of the exposed liner oxide. The liner oxide is then removed by applying a wet etch, contact regions to the gate electrode are salicided.
1. A method of reducing an etch rate of a layer of liner oxide for a gate electrode, comprising the steps of:
providing a substrate, a gate electrode formed over said substrate, a liner oxide formed over said substrate and on sidewalls of said gate electrode, and a gate spacer formed on a portion of said liner oxide so that said liner oxide has an exposed surface not covered by said gate spacer;
nitridizing said exposed surface of said liner oxide so as to form a layer of silicon oxy-nitride overlying said exposed surface of said liner oxide, said nitridizing step comprising an N 2 /H 2 plasma exposure;
removing a portion of said liner oxide not covered by said gate spacers and not covered by said layer of silicon oxy-nitride; and
saliciding contact points to said gate electrode.
2. The method of claim 1 , wherein said nitridizing step comprising a N 2 /H 2 plasma exposure is applied to a first and second surface.
3. The method of claim 1 , wherein a gate oxide is formed over said substrate, said gate oxide created to a thickness between about 50 and 150 Angstrom.
4. The method of claim 1 , wherein said gate electrode comprises polysilicon.
5. The method of claim 4 , wherein said gate electrode is deposited to a thickness between about 3,000 and 7,000 Angstrom.
6. The method of claim 1 , wherein said liner oxide has a thickness between about 100 and 500 Angstrom.
7. The method of claim 1 , wherein said saliciding contact with said gate electrode is a cobalt base process of salicidation.
8. A method of reducing an etch rate of a layer of liner oxide for a gate electrode, comprising the steps of:
providing a substrate, a gate electrode formed over said substrate, a liner oxide formed over said substrate and on sidewalls of said gate electrode, and a gate spacer formed on a portion of said liner oxide so that said liner oxide has an exposed surface not covered by said gate spacer;
nitridizing said exposed surface of said liner oxide so as to form a layer of silicon oxy-nitride overlying said exposed surface of said liner oxide, said nitridizing step comprising an N 2 ,H 2 plasma exposure;
removing a portion of said liner oxide not covered by said gate spacer and not covered by said layer of silicon oxy-nitride to leave a portion of said liner oxide beneath said gate spacers substantially without forming undercuts under said gate spacer; and
saliciding contact points to said gate electrode.
9. The method of claim 8 , wherein a gate oxide is formed over said substrate, said gate oxide having a thickness between about 50 and 150 Angstrom.
10. The method of claim 8 , wherein said gate electrode comprises polysilicon.
11. The method of claim 10 , wherein said gate electrode is deposited to a thickness between about 3,000 and 7,000 Angstrom.
12. The method of claim 8 , wherein said liner oxide has a thickness between about 100 and 500 Angstrom.
13. The method of claim 8 , wherein said saliciding contact with said gate electrode is a cobalt base process of salicidation.
14. The method of claim 8 , wherein said nitridizing step comprising a N 2 /H 2 plasma exposure is applied to a first and second surface of said liner oxide.
15. A method of reducing an etch rate of a layer of liner oxide for a gate electrode, comprising the steps of:
providing a substrate, a gate electrode formed over said substrate, a liner oxide formed over said substrate and on sidewalls of said gate electrode, and a gate spacer formed on a portion of said liner oxide so that said liner oxide has an exposed surface not covered by said gate spacer;
nitridizing said exposed surface of said liner oxide so as to form a layer of silicon oxy-nitride overlying an exposed surface of said gate electrode, said nitridizing step comprising an N 2 /H 2 plasma exposure;
removing a portion of said liner oxide not covered by said gate spacer and not covered by said layer of silicon oxy-nitride substantially without forming divots in said liner oxide beneath said gate spacer; and
saliciding contact points to said gate electrode.
16. The method of claim 15 , wherein said nitridizing step comprising a N 2 /H 2 plasma exposure is applied to a first and second surface of said liner oxide.
17. The method of claim 15 , wherein gate oxide is formed over said substrate, said gate oxide has a thickness between about 50 and 150 Angstrom.
18. The method of claim 15 , wherein said electrode comprises polysilicon.
19. The method of claim 18 , wherein said gate electrode is deposited to a thickness between about 3,000 and 7,000 Angstrom.
20. The method of claim 15 , wherein said liner oxide has a thickness between about 100 and 500 Angstrom.
21. The method of claim 15 , wherein said saliciding contact with said gate electrode is a cobalt base process of salicidation.