Semiconductor memory device and method of manufacturing the same
In one embodiment, a plurality of contact holes are formed using an self-aligned contact (SAC) process to expose active regions. When storage node contact or BC pads are formed in the contact holes, a conductive layer is partially filled in the contact holes to expose the sidewall of an interlayer insulating layer pattern over the BC pads. The exposed sidewall of the interlayer insulating layer pattern is covered with an etch stop spacer. Also, the top surface of the interlayer insulating layer pattern is covered with an etch stop layer. Then, a plurality of bit line contact or BC plugs are formed to contact the tops of the BC pads. A protruded region, which extends in one direction, is preferably formed on the sidewall of the contact plug.
1. A semiconductor memory device comprising:
a semiconductor substrate having a plurality of active regions defined therein;
a plurality of gate lines extending across the plurality of active regions, the plurality of gate lines including at least two adjacent gate lines;
a capping layer covering top surfaces and sidewalls of the gate lines;
a plurality of contact pads contacting the active regions between the at least two adjacent gate lines;
a first interlayer insulating layer pattern disposed between the plurality of gate lines;
a second interlayer insulating layer pattern disposed overlying the capping layer and the first interlayer insulating layer pattern, the second interlayer insulating layer pattern having a plurality of contact holes therethrough to expose top surfaces of the contact pads, the second interlayer insulating layer pattern having a top surface and a sidewall;
a first etch stop layer pattern covering the top surface of the second interlayer insulating layer pattern;
a second etch stop layer pattern disposed over a portion of the contact pad to cover the sidewall of the second interlayer insulating layer pattern; and
a plurality of contact plugs extending through the contact holes to contact the top surfaces of the contact pads,
wherein the first and second etch slop layer patterns each having an etch selectivity with respect to the second interlayer insulating layer pattern.
2. The device of claim 1 , wherein at least one of the contact plugs has one protruded region over the first etch stop layer pattern.
3. The device of claim 2 , wherein the protruded region is disposed on one of two gate lines on both sides of the at least one of the contact plugs.
4. The device of claim 3 , wherein the at least one of the contact plugs has a recessed region adjacent to the other of the two gate lines on both sides of the at least one of the contact plugs, wherein the recessed region has a shape corresponding to that of the protruded region.
5. The device of claim 3 , wherein the plurality of contact plugs include a series of contact plugs which are arranged in one column,
wherein protruded regions of the series of contact plugs extend in an opposite direction from protruded regions of adjacent contact plugs among the series of contact plugs.
6. The device of claim 3 , wherein the plurality of contact plugs include a series of contact plugs which are arranged in one row,
wherein protruded regions of the series of contact plugs extend in the same direction as protruded regions of adjacent contact plugs among the series of contact plugs.
7. The device of claim 1 , wherein the first etch stop layer pattern has a thickness of about 50 Å to about 500 Å.
8. The device of claim 1 , wherein the second etch stop layer pattern covers the sidewall of the second insulating layer pattern to a thickness of about 50 Å to about 500 Å.
9. The device of claim 1 , further comprising a plurality of lower electrodes, which respectively contact the contact plugs and are arranged to be in a zigzag pattern.
10. The device of claim 9 , further comprising a plurality of bit lines extending across the gate lines,
wherein the plurality of lower electrodes are formed over the bit lines.
11. The device of claim 1 , wherein the first etch stop layer patterns is formed of nitride.
12. The device of claim 1 , wherein the second etch stop layer pattern is formed of nitride.
13. The device of claim 1 , wherein the second interlayer insulating layer pattern is formed of oxide.