IP Library › Granted Patent US 6,921,958
Granted Patent B2
US 6,921,958 · App. 10/689,058 · Granted Jul 26, 2005

IGBT with a Schottky barrier diode

Assignee: Mitsubishi Denki Kabushiki Kaisha
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Quick Facts
Patent No.
US 6,921,958
App. No.
10/689,058
Granted
Jul 26, 2005
Kind
B2
Abstract

A semiconductor device which IGBT (Z 1 ) and a control circuit (B 1 ) for driving the IGBT (Z 1 ) are formed on the same semiconductor substrate by using a junction isolation technology, includes an input terminal (P 1 ) for inputting a drive signal of the IGBT (Z 1 ), a Schottky barrier diode (D 2 ) having an anode connected to the input terminal (P 1 ) and a cathode connected to an input terminal (B 11 ) of the control circuit (B 1 ), and a p-channel MOSFET (T 1 ) for shorting both ends of the Schottky barrier diode (D 2 ) when the voltage of the drive signal input to the input terminal (P 1 ) is higher than a predetermined voltage, thereby latch-up of the parasitic element is prevented and a transmission loss of the input signal can be reduced.

Claims (8)

1. A semiconductor device on which an insulated gate bipolar transistor and a control circuit for driving the insulated gate bipolar transistor are formed on a same semiconductor substrate, comprising:

an input terminal via which a drive signal of the insulated gate bipolar transistor is input;

a Schottky barrier diode having an anode connected to the input terminal and a cathode connected to an input terminal of the control circuit; and

a first p-channel MOSFET that shorts both ends of the Schottky barrier diode when the voltage of the drive signal input to the input terminal is higher than a predetermined voltage.

2. The semiconductor device according to claim 1 , further comprising a resistor which is interposed between the cathode of the Schottky barrier diode and the input terminal of the control circuit.

3. The semiconductor device according to claim 1 , further comprising a second p-channel MOSFET which is serially connected between the cathode of the Schottky barrier diode and the input terminal of the control circuit.

4. The semiconductor device according to claim 1 , wherein a series circuit of a resistor and a second p-channel MOSFET is connected between the gate and the emitter of the insulated gate bipolar transistor.

5. The semiconductor device according to claim 1 , further comprising a CMOS inverter circuit having an output terminal connected to the gate of the first p-channel MOSFET, wherein a signal depending on a signal level of the drive signal input via the input terminal is input to the input terminal of the CMOS inverter circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2003
From: YASUDA, YUKIO
To: MITSUBISHI DENKI KABUSHIKI KAISHA
Reel/Frame 014628/0808 →
Priority Claims (1)
JP 2002-362133 · Dec 13, 2002 · national
Continuity (1)
Related Publication 20040113172A1 · Jun 17, 2004