Increasing carrier mobility in NFET and PFET transistors on a common wafer
View Patent ↗Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop layers, overlying the transistors with stress being wholly or partially relieved in portions of the respective layers, preferably by implantations with heavy ions such as germanium, arsenic, xenon, indium, antimony, silicon, nitrogen oxygen or carbon in accordance with a block-out mask. The distribution and small size of individual areas of such stressed structures also prevents warping or curling of even very thin substrates.
1. A method of adjusting carrier mobility for different semiconductor conductivities on the same chip comprising steps, in sequence, of:
forming a first layer of material applying a first stress level on a first portion of a surface of a chip,
selectively reducing said first stress level of a portion of said first layer of material, thereby reducing said first stress level on said first portion,
forming a second layer of material applying a second stress level on a second portion of a surface of the chip said second stress level being different from said first stress level, and
selectively reducing said second stress level of a portion of said second layer of material, thereby reducing said second stress level on said second portion.
2. The method as recited in claim 1 , wherein said first stress level is tensile and said second stress level is compressive.
3. The method as recited in claim 1 , wherein said step of providing a first layer is performed by plasma enhanced chemical vapor deposition.
4. The method as recited in claim 3 , wherein said first stress level is developed in accordance with plasma power during said plasma enhanced chemical vapor deposition.
5. The method as recited in claim 1 , wherein said step of providing said second layer is performed by thermal chemical vapor deposition.
6. The method as recited in claim 5 , wherein said step of providing a first layer is performed by plasma enhanced chemical vapor deposition.
7. The method as recited in claim 6 , wherein said first stress level is developed in accordance with plasma power during said plasma enhanced chemical vapor deposition.
8. The method as recited in claim 1 , wherein one of said first layer of material and said second layer of material is silicon nitride or silicon oxynitride.
9. The method as recited in claim 1 , including the further step of:
forming two transistors in said portion of a surface of a chip prior to said steps of providing said first and second layers of material.
10. The method as recited in claim 1 , wherein said step of providing a second layer of material results in a greater thickness than a thickness resulting for said step of providing a first layer of material.
11. The method as recited in claim 1 , wherein said steps of reducing stress are performed by implanting ions of germanium, arsenic, xenon, indium, antimony, silicon, nitrogen, oxygen or carbon.