IP Library › Granted Patent US 6,943,080
Granted Patent B2
US 6,943,080 · App. 10/718,726 · Granted Sep 13, 2005

Method of manufacturing the semiconductor device

Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 6,943,080
App. No.
10/718,726
Granted
Sep 13, 2005
Kind
B2
Abstract

A method of manufacturing semiconductor device including a capacitor including a pair of electrodes and a ferroelectric flu with ferroelectricity sandwiched therebetween, by depositing the ferroelectric film on first substrate; forming the capacitor by grinding the ferroelectric film and forming the electrodes so that the electrodes are perpendicular to a direction of a polarization axis of the ferroelectric film; forming a first interlayer insulating film covering a surface of the first substrate and the capacitor; forming a transistor on a second substrate, the transistor including a ate electrode and a diffusion region; forming a second interlayer insulating film covering a surface of the second substrate and the transistor; flattening surfaces of the first and second interlayer insulating films by chemical mechanical polishing; integrating the first and second substrates by joining the flattened surfaces of the first and second interlayer insulating films; and removing the first substrate.

Claims (24)

1. A method of manufacturing a semiconductor device including a capacitor including a pair of electrodes and a ferroelectric film with ferroelectricity sandwiched therebetween, the method comprising the steps of:

(a) depositing the ferroelectric film on a first substrate;

(b) forming the capacitor by grinding the ferroelectric film and forming the electrodes so that the electrodes are perpendicular to a direction of a polarization axis of the ferroelectric film;

(c) forming a first interlayer insulating film covering a surface of the first substrate and the capacitor;

(d) forming a transistor on a second substrate, the transistor including a gate electrode and a diffusion region;

(e) forming a second interlayer insulating film covering a surface of the surface of the second substrate and the transistor;

(f) flattening surfaces of the first and second interlayer insulating films by chemical mechanical polishing;

(g) integrating the first and second substrates by joining the flattened surfaces of the first and second interlayer insulating film; and

(h) removing the first substrate.

2. The method as claimed in claim 1 , wherein the first substrate employs one of a (100) surface and a (010) surface thereof as a main surface.

3. The method as claimed in claim 2 , wherein the first substrate has an inclination with an offset angle from the one of the (100) surface and the (010) surface thereof.

4. The method as claimed in claim 2 , wherein the first substrate comprises MgO, SrTiO 3 , α-Al 2 O 3 , or MgAl 2 O 4 .

5. The method as claimed in claim 1 , wherein:

a buffer layer is formed on the first substrate;

the first substrate comprises a Si substrate; and

the buffer layer comprises a MgO layer, an yttrium-stabilized ZrO 2 layer, a SrTiO 3 layer, a MgAl 2 O 4 layer, or a CaO layer.

6. The method as claimed in claim 5 , wherein:

an additional buffer layer is formed on the buffer layer;

the buffer layer comprises MgO layer; and

the additional buffer layer comprises a SrRuO 3 layer, a YBa 2 Cu 3 O 7−δ layer, or a La 2−x Sr x CuO 4 layer.

7. The method as claimed in claim 1 , wherein:

a buffer layer is formed one first substrate;

the first substrate comprises a Si substrate; and

the buffer layer comprises a SrRuO 3 layer, a YBa 2 Cu 3 O 7−δ layer, or a La 2−x Sr x CuO 4 layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 24, 2003
From: MARUYAMA, KENJI
To: FUJITSU LIMITED
Reel/Frame 014737/0844 →
Priority Claims (1)
JP 2002-358093 · Dec 10, 2002 · national
Continuity (1)
Related Publication 20040108531A1 · Jun 10, 2004