Semiconductor device and method for manufacturing the same
A semiconductor device and a method for forming the same. A dielectric layer is formed on a semiconductor substrate or on a lower electrode of a capacitor. Vacuum annealing is performed on the dielectric layer. Thus, impurities remaining in the dielectric layer can be effectively removed, and the dielectric layer can be densified. As a result, the electrical characteristics of the semiconductor device are improved. For example, the leakage current characteristics of the dielectric layer are improved and capacitance is increased.
1. A method for forming a capacitor, the method comprising:
forming a lower electrode on a semiconductor substrate;
forming a dielectric layer on the lower electrode;
vacuum annealing the dielectric layer; and
forming an upper electrode on the dielectric layer, wherein the vacuum annealing is performed on the dielectric layer at a temperature of about 200-850° C. in a chamber, while evacuating the chamber to a high vacuum level of about 1×10 −8 −1 torr.
2. The method of claim 1 , wherein the lower electrode is a single layer of doped polysilicon, TiN, TaN, WN, Ru, Ir, or Pt, or a composite layer of doped polysilicon, TiN, TaN, WN, Ru, Ir, or Pt.
3. The method of claim 1 , wherein the dielectric layer is formed to a thickness of about 20-200 Å.
4. The method of claim 1 , wherein the dielectric layer comprises HfO 2 , Y 2 O 3 , Al 2 O 3 , TiO 2 , BaO, SrO, ZrO 2 , Ta 2 O 5 , Mb 2 O 5 or combinations thereof.
5. The method of claim 1 , wherein the vacuum annealing is performed without supplying an inert gas or a reactant gas onto the dielectric layer.
6. The method of claim 1 , wherein the temperature is about 700-800° C. when the lower electrode is formed of polysilicon, or about 400-600° C. when the lower electrode is formed of a metal nitride or a noble metal.
7. The method of claim 1 , wherein the upper electrode is formed by MOCVD, using a non-Cl-containing material as the source material.
8. The method of claim 1 , wherein the forming a dielectric comprises:
forming a first dielectric layer on the lower electrode; and
forming a second dielectric layer on the first dielectric layer.
9. The method of claim 8 , wherein the first dielectric layer has a dielectric constant lower than that of the second dielectric layer.
10. The method of claim 8 , wherein the first dielectric layer is an Al 2 O 3 dielectric layer.
11. The method of claim 10 , wherein the Al 2 O 3 dielectric layer is formed to a thickness of about 20-60 Å.
12. The method of claim 10 , wherein the second dielectric layer is an HfO 2 dielectric layer.
13. The method of claim 12 , wherein the HfO 2 dielectric layer is formed to a thickness of about 10-40 Å.
14. The method of claim 12 , wherein the thickness of the Al 2 O 3 dielectric layer is greater than that of the HfO 2 dielectric layer.
15. The method of claim 8 , after vacuum annealing, further comprising thermally treating the second dielectric layer in an O 3 or O 2 plasma condition.
16. The method of claim 15 , wherein the thermal treating in an O 3 or O 2 plasma condition is performed at a temperature of about 200-600° C.
17. The method of claim 16 , wherein the thermal treating is performed at about 300-400° C.
18. The method of claim 15 , wherein the second dielectric layer is thermally treated at a pressure of about 5-50 torr in the O 3 plasma condition, or at a pressure of about 0.1-5 torr in the O 2 plasma condition.
19. The method of claim 8 , before vacuum annealing, further comprising thermally treating the second dielectric layer in an O 3 or O 2 plasma condition.
20. A method for forming a capacitor, the method comprising:
forming a lower electrode on a semiconductor substrate;
forming a dielectric layer on the lower electrode;
forming a Cl barrier layer on the dielectric layer; and
forming an upper electrode on the Cl barrier layer.
21. The method of claim 20 , before forming the Cl barrier layer, further comprising vacuum annealing the dielectric layer.
22. The method of claim 21 , wherein the vacuum annealing is performed on the dielectric layer at a temperature of about 200-850° C. in a chamber, while evacuating the chamber to a high vacuum level of about 1×10 −8 −1 torr.
23. The method of claim 20 , wherein the dielectric layer is an HfO 2 dielectric layer.
24. The method of claim 23 , wherein the HfO 2 dielectric layer is formed to a thickness of about 20-80 Å.
25. The method of claim 20 , wherein the Cl barrier layer comprises Al 2 O 3 , Ta 2 O 5 , SiO 2 , or Si 3 N 4 .
26. The method of claim 20 , wherein the Cl barrier layer is formed to a thickness of about 3-50 Å.
27. The method of claim 26 , wherein the Cl barrier layer is formed to a thickness of about 10-20 Å.
28. The method of claim 20 , wherein the Cl barrier layer comprises Al 2 O 3 by CVD.
29. The method of claim 28 , wherein the Cl barrier layer is deposited, using TMA, AlCl 3 , AlH 3 N(CH 3 ) 3 , C 6 H 15 AlO, (C 4 H 9 ) 2 AlH, (CH 3 ) 2 AlCl, (C 2 H 5 ) 3 Al, or (C 4 H 9 ) 3 Al and H 2 O at a temperature of about 400-500° C. and a pressure of about 1-5 torr.
30. The method of claim 20 , wherein the Cl barrier layer is formed of Al 2 O 3 by ALD.
31. The method of claim 30 , wherein the Cl barrier layer is deposited using TMA as a first reactant and O 3 , H 2 O, or plasma N 2 O, plasma O 2 as a second reactant.
32. The method of claim 31 , wherein the deposition is performed at a temperature of about 250-400° C. and a pressure of about 1-5 torr.
33. The method of claim 20 , further comprising thermally treating the resultant structure having the Cl barrier layer in an O 3 or O 2 plasma condition at a temperature of about 250-400° C.
34. The method of claim 33 , wherein the temperature is about 300-400° C.
35. The method of claim 33 , wherein the Cl barrier layer is thermally treated at a pressure of about 5-50 torr in the O 3 plasma condition, or at a pressure of about 0.1-5 torr in the O 2 plasma condition.
36. The method of claim 23 , further comprising:
forming an Al 2 O 3 dielectric layer on the lower electrode before forming an HfO 2 dielectric layer.
37. The method of claim 36 , wherein the Al 2 O 3 dielectric layer prevents the lower electrode from being oxidized during subsequent thermal treatment on the dielectric layer.
38. The method of claim 20 , wherein the upper electrode is formed to a thickness of about 50-2000 Å, using a Cl-containing source material.
39. A method for forming a semiconductor device, the method comprising:
forming a dielectric layer on a semiconductor substrate; and
vacuum annealing the dielectric layer, wherein the vacuum annealing is performed on the dielectric layer at a temperature of about 200-850° C. in a chamber, while evacuating the chamber to a high vacuum level of about 1×10 −8 −1 torr.
40. The method of claim 39 , further comprising forming a gate electrode on the vacuum annealed dielectric layer.
41. The method of claim 39 , wherein the dielectric layer is a single layer of Y 2 O 3 , Al 2 O 3 , TiO 2 , BaO, SrO, ZrO 2 , Ta 2 O 5 , Mb 2 O 5 or a composite layer of Y 2 O 3 , Al 2 O 3 , TiO 2 , BaO, SrO, ZrO 2 , Ta 2 O 5 , Mb 2 O 5 .