Composite spacer liner for improved transistor performance

1. A method of manufacturing a semiconductor device, the method comprising:

forming a gate electrode, having side surfaces, over an upper surface of a substrate with a gate dielectric layer therebetween;

depositing an oxide liner, by decoupled plasma deposition at a temperature no greater than about 400° C., on the side surface of the gate electrode and the upper surface of the substrate;

depositing a nitride liner, at a thickness of about 50 Å to about 200 Å, on the oxide liner by decoupled plasma deposition at a temperature no greater than about 400° C.; and

forming a sidewall spacer on the nitride liner.

2. The method according to claim 1 , wherein:

the oxide liner comprises a silicon oxide;

the nitride liner comprises a silicon nitride; and

the sidewall spacer comprises a silicon oxide, silicon nitride or silicon oxynitride.

3. The method according to claim 2 , comprising forming the sidewall spacer of a silicon oxide having a dielectric constant (k) no greater than about 3.9.

4. The method according to claim 2 , further comprising ion implanting to form shallow source/drain extensions in the upper surface of the substrate, using the gate electrode as a mask, before depositing the oxide liner.

5. The method according to claim 4 , comprising ion implanting a P-type impurity to form the source/drain extension.

6. The method according to claim 5 , wherein the P-type impurity comprises boron.

7. The method according to claim 6 , comprising forming the source/drain extensions at a junction depth (X j ) of about 200 Å to about 300 Å.

8. The method according to claim 2 , comprising:

depositing the silicon oxide liner at a thickness of about 10 Å to about 50 Å.