IP Library › Granted Patent US 6,956,265
Granted Patent B2
US 6,956,265 · App. 10/675,950 · Granted Oct 18, 2005

Semiconductor device and method for manufacturing partial SOI substrates

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 6,956,265
App. No.
10/675,950
Granted
Oct 18, 2005
Kind
B2
Abstract

There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate being provided with a boundary region formed between the SOI region and the non-SOI region and having a second insulating film buried therein, the second insulating film being inclined upward from the SOI region side toward the non-SOI region side, the second insulating film having a thickness smaller than the thickness of the first insulating film and being tapered from the SOI region side to the non-SOI region side, a pair of element isolating insulating regions separately formed in the non-SOI region of semiconductor substrate and defining element regions, a pair of impurity diffusion regions formed in the element regions, and a gate electrode formed via a gate insulating film in the element region of the semiconductor substrate.

Claims (11)

1. A semiconductor device comprising:

a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, said semiconductor substrate being provided with a boundary region formed between said SOI region and said non-SOI region and having a second insulating film buried therein, said second insulating film being inclined upward from the SOI region side toward the non-SOI region side, said second insulating film having a thickness which is smaller than the thickness of said first insulating film and being tapered from the SOI region side to the non-SOI region side;

a pair of element isolating insulating regions separately formed in said non-SOI region of semiconductor substrate and defining element regions;

a pair of impurity diffusion regions formed in said element regions and in contact with said element isolating insulating regions, respectively; and

a gate electrode formed via a gate insulating film in the element region of said semiconductor substrate.

2. The semiconductor device according to claim 1 , wherein said second insulating film formed in said boundary region of said semiconductor substrate is buried as a continuous film all along the lateral direction of said boundary region.

3. The semiconductor device according to claim 1 , wherein said second insulating film formed in said boundary region of said semiconductor substrate is intermittently formed in said boundary region.

4. The semiconductor device according to claim 1 , wherein the width of said boundary region in said semiconductor substrate is within the range of 1 to 5 μm.

5. The semiconductor device according to claim 1 , wherein the distance from one end of said boundary region located on the non-SOI region side to said impurity diffusion region is 0.5 μm or more.

6. The semiconductor device according to claim 1 , wherein said semiconductor substrate is a silicon substrate.

7. The semiconductor device according to claim 1 , wherein said first insulating film and said second insulating film are both formed of a silicon oxide film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2004
From: NAGANO, HAJIME; MIZUSHIMA, ICHIRO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 014932/0438 →
Priority Claims (1)
JP 2003-283479 · Jul 31, 2003 · national
Continuity (1)
Related Publication 20050023609A1 · Feb 3, 2005