Circuit and method for improving instruction fetch time from a cache memory device
View Patent ↗A circuit and method are contemplated herein for improving instruction fetch time by determining mapping information prior to storage of the mapping information in a lower-level memory device. In one embodiment, the circuit and method are adapted to format and align the prefetched instructions into predecoded instructions, and determine mapping information relating the prefetched instructions to the predecoded instructions. In addition, the circuit and method may be adapted to store the mapping information along with corresponding predecoded instructions. By determining the mapping information prior to storage of the mapping information within the lower-level memory device, the circuit and method advantageously increases the rate at which the predecoded instructions may be fetched from the lower-level memory device.
1. A circuit adapted to receive one or more variable length instructions from a memory device via a prefetch unit, the circuit comprising:
a predecoding unit coupled to align and format the one or more variable length instructions into one or more predecoded instructions, wherein the predecoding unit is configured to determine mapping information relating the one or more variable length instructions to the one or more predecoded instructions;
wherein the mapping information comprises;
an adjust field comprising a shift value for each of the one or more variable length instructions;
a valid field comprising a logic value indicating an occupied position for each of the one or more predecoding instructions within a predecoded instruction field; and
a cache memory device coupled to store the mapping information and the predecoded instruction field, comprising the one or more predecoded instructions in a first contiguous portion of the cache memory device.
2. The circuit recited in claim 1 , wherein the predecoding unit comprises an adjust field detector coupled to determine the shift values, wherein the shift values map the one or more variable length instructions to corresponding positions in the predecoded instruction field.
3. The circuit recited in claim 2 , wherein the adjust field detector comprises a look-up table relating a starting position for each of the one or more variable length instructions to a corresponding shift value.
4. The circuit recited in claim 3 , wherein the predecoding unit further comprises alignment circuitry coupled to format and align the one or more variable length instructions using the starting positions.
5. The circuit recited in claim 1 , wherein the circuit further comprises configuration circuitry coupled to receive the first contiguous position, a second contiguous portion, and a pointer value representing one instruction of the one or more variable length instructions.
6. The circuit recited in claim 5 , wherein the configuration circuitry comprises:
a first multiplexer coupled to select one shift value from the first contiguous portion, wherein the one shift value locates a predecoded instruction stored within the first contiguous portion that corresponds to the one instruction;
a second multiplexer coupled to append the predecoded instructions to a segment of the second contiguous portion into an appended instruction field, wherein the segment comprises a number of predecoded instructions equal to a number of unoccupied positions in the valid field; and
a shift register coupled to shift the appended instruction field by the one shift value.
7. A method for predecoding one or more variable length instructions prefetched from a memory device, the method comprising:
formatting and aligning the one or more variable length instructions into one or more predecoded instructions arranged within a predecoded instruction field;
determining an adjust field comprising shift values for mapping the one or more variable length instructions to corresponding predecoded instructions within the predecoded instruction field;
determining a valid field comprising a logic value indicating an occupied position for each of the one or more predecoded instructions in the predecoded instruction field; and
storing the adjust field, the predecoded instruction field and the valid field within contiguous portions of a cache memory device.
8. The method as recited in claim 7 , further comprising detecting a bit pattern within the one or more variable length instructions to determine a starting position for each of the one or more variable length instruction.
9. The method as recited in claim 8 , wherein the step of detecting a bit pattern comprises using a state machine to determine the starting position.
10. The method as recited in claim 8 , wherein the step of determining the adjust field comprises using a lookup table to select the adjust field corresponding to the starting positions for each of the one or more variable length instructions.
11. The method as recited in claim 7 , wherein the step of formatting and aligning comprises formatting the one or more variable instructions into one or more fixed length instructions and aligning the one or more fixed length instructions into the predecoded instruction field.
12. A method for decoding one or more contiguous portions of a cache memory device, the method comprising:
receiving a first portion and a second portion of the one or more contiguous portions from the cache memory device, wherein the one or more contiguous portions each comprise a valid field, an adjust field, and a predecoded instruction field;
selecting one or more predecoded instructions from the predecoded instruction field of the first portion; and
selecting a next predecoded instruction to be executed by a processing unit from the one or more predecoded instructions of the first portion.
13. The method as recited in claim 12 , wherein the step of selecting one or more predecoded instructions comprises determining an occupied position within the predecoded instruction field by detecting one or more logic values within the valid field of the first portion.
14. The method as recited in claim 13 , wherein the step of selecting one or more predecoded instructions further comprises detecting one or more opposite logic values within the valid field of the first portion to select one or more predecoded instructions in the second portion.
15. The method as recited in claim 14 , wherein the step of selecting one or more predecoded instructions further comprises appending the selected predecoded instructions of the second portion to the selected predecoded instructions of the first portion into an appended instruction field.
16. The method as recited in claim 12 , wherein the step of selecting the next predecoded instruction comprises selecting a shift value from a plurality of shift values within the adjust field of the first portion.
17. The method as recited in claim 15 , wherein the step of selecting a shift value comprises inputting a pointer value into a multiplexer configured to receive the plurality of shift values.
18. The method as recited in claim 17 , wherein the pointer value comprises a program counter value.
19. The method as recited in claim 15 , wherein the step of selecting the next predecoded instruction further comprises shifting the appended instruction field by the selected shift value to place the next predecoded instruction into a first position of the appended instruction field.