Isolation structure with nitrogen-containing liner and methods of manufacture
View Patent ↗A semiconductor isolation trench includes a substrate and a trench formed therein. The trench is lined with a nitrogen-containing liner and filled with a dielectric material. The nitrogen-containing liner preferably contacts the active region of a device, such as a transistor, located adjacent to the trench.
1. A method of forming an isolation structure, the method comprising:
providing a substrate having a trench formed therein, the trench having at least one rounded corner;
applying a first nitrogen-containing liner on a top surface of the substrate and the trench;
forming a trench-filling material over the first nitrogen-containing liner, the trench-filling material substantially filling the trench; and
removing a first portion of the first nitrogen-containing liner and the trench-filling material such that a second portion of the first nitrogen-containing liner and trench-filling material remains within the trench.
2. The method of claim 1 , wherein the step of providing a substrate includes:
applying a mask layer to the substrate;
patterning the mask layer such that the patterned mask layer defines the trench;
etching the mask layer and the substrate to form the trench in the substrate; and
removing the mask layer.
3. The method of claim 2 , wherein the mask layer comprises a silicon nitride mask layer.
4. The method of claim 2 , further comprising rounding the corners of the trench after etching the substrate.
5. The method of claim 4 , wherein the rounding the corners of the trench comprises rounding the corners by annealing the substrate in a gaseous ambient.
6. The method of claim 4 , wherein the rounding the corners of the trench comprises rounding the corners by annealing the substrate in a gaseous ambient comprising hydrogen, nitrogen, helium, neon, argon, xenon, or a combination thereof.
7. The method of claim 4 , wherein the rounding the corners of the trench comprises rounding the corners by annealing the substrate in a gaseous ambient, wherein the annealing is performed at a temperature of about 700 to about 950 degrees Celsius.
8. The method of claim 4 , wherein the rounding the corners of the trench comprises rounding the corners by annealing the substrate in a gaseous ambient, wherein the annealing is performed at a pressure of about 1 Torr to about 1000 Torr.
9. The method of claim 4 , wherein the rounding the corners of the trench comprises creating rounded corners having a radius of curvature of about 5 nm to about 50 nm.
10. The method of claim 1 , wherein the first nitrogen-containing liner comprises Si 3 N 4 .
11. The method of claim 1 , wherein the first nitrogen-containing liner comprises silicon oxynitride.
12. The method of claim 1 , wherein the first nitrogen-containing liner has a nitrogen content about 5 of about 60 percent.
13. The method of claim 1 , wherein the first nitrogen-containing liner has a thickness in the range of about 5 to about 200 angstroms.
14. The method of claim 1 , wherein the trench-filling material is a dielectric.
15. The method of claim 14 , wherein the trench-filling material comprises silicon oxide.
16. The method of claim 1 , wherein the removing is performed at least in part by planarizing the trench-filling material.
17. The method of claim 16 , wherein the planarizing step is a chemical mechanical polishing step.
18. The method of claim 1 , further comprising forming transistors in close proximity to the trench.
19. The method of claim 1 , further comprising:
forming transistors on the substrate in close proximity to the trench;
depositing an inter-layer dielectric over the transistors; and
depositing a metal line on the inter-layer dielectric.
20. The method of claim 19 , wherein the inter-layer dielectric comprises silicon oxide.
21. The method of claim 19 , wherein the metal line comprises aluminum, copper, tungsten, or a combination thereof.
22. A method of forming an isolation structure, the method comprising:
providing a substrate having a trench formed therein and a patterned mask thereon, the patterned mask overlies portions of the substrate adjacent to the trench;
etching a portion of the patterned mask to pull-back the patterned mask from an edge of the trench;
annealing the substrate in a gaseous ambient to form rounded corners on the trench;
forming a nitrogen-containing liner over the trench and the patterned mask;
filling the trench with a trench-filling material;
exposing the nitrogen-containing liner over the patterned mask;
removing a portion of the nitrogen-containing liner overlying the patterned mask; and
removing the patterned mask.
23. The method of claim 22 , further comprising forming transistors on the substrate in close proximity to the trench.
24. The method of claim 22 , further comprising:
forming transistors in a region of the substrate adjacent to the trench;
forming an inter-layer dielectric over the transistors; and
forming a metal line over the inter-layer dielectric.
25. The method of claim 24 , wherein the inter-layer dielectric comprises silicon oxide.
26. The method of claim 24 , wherein the metal line comprises aluminum, copper, tungsten, or a combination thereof.
27. The method of claim 22 , wherein the patterned mask comprises a silicon nitride layer overlying a silicon dioxide layer.
28. The method of claim 22 , wherein the rounded corners have a radius of curvature of about 5 to about 50 nm.
29. The method of claim 22 , wherein the annealing step is performed at a temperature of about 700 to about 950 degrees Celsius.
30. The method of claim 22 , wherein the gaseous ambient comprises hydrogen, nitrogen, helium, neon, argon, xenon, or a combination thereof.
31. The method of claim 22 , wherein the annealing is performed at a pressure of about 1 to 1000 Torr.
32. The method of claim 22 , wherein the nitrogen-containing liner comprises silicon nitride or silicon oxynitride.
33. The method of claim 22 , wherein the nitrogen-containing liner has a nitrogen content of about 5 to 60 percent.
34. The method of claim 22 , wherein the nitrogen-containing liner has a thickness of about 5 to 200 angstroms.
35. The method of claim 22 , wherein the trench-filling material is a dielectric.
36. The method of claim 22 , wherein the trench-filling material comprises silicon oxide.
37. The method of claim 22 , further comprising planarizing to remove a portion of the trench-filling material.
38. The method of claim 22 , further comprising planarizing to remove a portion of the trench-filling material, wherein the planarizing is performed by chemical mechanical polishing.
39. A method of forming an isolation structure, the method comprising:
providing a semiconductor substrate having a top surface and having a trench formed therein, the trench having rounded corners in a top portion and having rounded corners in a bottom portion;
forming nitrogen-containing liner over the trench and the top surface;
filling the trench with a trench-filling material;
planarizing the trench-filling material such that the nitrogen-containing liner remains; and
removing the nitrogen-containing liner overlying the top surface.
40. The method of claim 39 , further comprising forming transistors in a region of the semiconductor substrate adjacent to the trench.
41. The method of claim 40 , further comprising:
forming an inter-layer dielectric over the transistors; and
forming a metal line on the inter-layer dielectric.
42. The method of claim 41 , wherein the inter-layer dielectric comprises silicon oxide.
43. The method of claim 41 , wherein the metal line comprises aluminum, copper, tungsten, or a combination thereof.
44. The method of claim 39 , wherein the rounded corners have a radius of curvature in the range of about 5 to about 50 nm.
45. The method of claim 39 , wherein the providing the semiconductor substrate includes:
forming a patterned mask over the semiconductor substrate;
forming a trench in a portion of the semiconductor substrate not covered by the patterned mask;
removing the patterned mask; and
annealing the semiconductor substrate in a gaseous ambient to form the rounded corners.
46. The method of claim 45 , wherein the annealing the semiconductor substrate is performed at a temperature in the range of about 700 to about 950 degrees Celsius.
47. The method of claim 45 , wherein the gaseous ambient comprises hydrogen, nitrogen, helium, neon, argon, xenon, or a combination thereof.
48. The method of claim 45 , wherein the annealing the semiconductor substrate is performed at a pressure in the range of about 1 Torr to about 1000 Torr.
49. The method of claim 39 , further comprising forming a silicon dioxide liner prior to forming the nitrogen-containing liner.
50. The method of claim 39 , wherein the nitrogen-containing liner comprises silicon nitride or silicon oxynitride.
51. The method of claim 39 , wherein the nitrogen-containing liner has a nitrogen content of about 5 to about 60 percent.
52. The method of claim 39 , wherein the nitrogen-containing liner has a thickness in the range of about 5 to about 200 angstroms.
53. The method of claim 39 , wherein the trench-filling material is a dielectric.
54. The method of claim 53 , wherein the trench-filling material comprises silicon oxide.
55. The method of claim 39 , wherein the planarizing the trench-filling material is performed by a chemical mechanical polishing process.
56. The method of claim 55 , wherein the chemical mechanical polishing process employs a slurry comprising of cerium oxide.