Semiconductor devices having DRAM cells and methods of fabricating the same
The present invention discloses a semiconductor device, comprising: bit line landing pads formed over a semiconductor substrate; storage landing pads formed on both sides of the bit line landing pads; a bit line interlayer insulator formed over the whole surface of the semiconductor substrate having the landing pads; a plurality of parallel bit line patterns arranged on the bit line interlayer insulator; bit line insulating layer patterns filling in gate regions between the bit line patterns; upper contact holes formed in the bit line insulating layer patterns to expose side walls of the bit line patterns and located higher than upper surfaces of the bit line patterns; contact hole spacers covering the side walls of the upper contact holes; lower contact holes penetrating the bit line insulating layer patterns and the bit line interlayer insulator below holes surrounded by the contact hole spacers to expose the storage node landing pads and self-alighed with the upper contact holes; and storage node contact plugs filling in the upper and lower contact holes.
1. A method of manufacturing a semiconductor device, comprising:
forming bit line and storage node landing pads over a semiconductor substrate;
forming a bit line interlayer insulating layer overlying the bit line and storage node landing pads;
forming a plurality of bit line patterns on the bit line interlayer insulating layer;
forming line insulating layer patterns filling gap regions between the bit line patterns;
forming a plurality of hard mask patterns traversing the bit line patterns over the line insulating layer patterns and the bit line patterns;
partially etching the line insulating layer patterns by using the hard mask patterns and the bit line patterns as an etching mask to form upper contact holes which expose side walls of the bit line patterns;
forming contact hole spacers on the side walls of the upper contact holes;
sequentially etching the line insulating patterns and the bit line interlayer insulating layer, using the contact hole spacers, the hard mask patterns and the bit line patterns as an etching mask to form lower contact holes which expose the storage node landing pads; and
forming storage node contact plugs filling the upper and lower contact holes.
2. The method of claim 1 , wherein the formation of the line insulating layer patterns comprises
forming a buried interlayer insulating layer overlying the bit line patterns; and
planarizing the buried interlayer insulating layer to expose upper surfaces of the bit line patterns.
3. The method of claim 1 , wherein the formation of the hard mask patterns comprises
forming a poly silicon layer overlying the bit line patterns and the line insulating layer pattern; and
patterning the poly silicon layer in a direction perpendicular to the bit line patterns to place over the bit line landing pads.
4. The method of claim 1 , wherein the formation of the hard mask patterns comprises
forming a silicon nitride layer on the bit line patterns and the line insulating layer pattern; and
patterning the silicon nitride layer in the direction substantially perpendicular to the bit line patterns to place over the bit line landing pads.
5. The method of claim 1 , wherein the formation of the contact hole spacers comprises:
conformally forming a silicon nitride layer overlying the upper contact holes; and
anisotropically etching the silicon nitride layer.
6. The method of claim 1 , wherein the formation of the lower contact holes comprises etching the line insulating patterns and the bit line interlayer insulating layer sequentially through the upper contact holes by using polymers generated by a reaction of an etching gas to the contact hole spacers, the line insulating layer patterns and the bit line interlayer insulating layer.
7. The method of claim 1 , wherein the formation of the storage node contact plug comprises:
forming a doped poly silicon layer to a predetermined thickness sufficient for filling the upper and lower contact holes on the hard mask patterns; and
planarizing the doped poly silicon layer to remove the hard mask patterns and to expose top surfaces of the bit line patterns.